Technical Reference Guide
Compaq iPAQ Family of Internet Devices
First Edition - March 2000
8-11
8.3 MEMORY DETECT ION AND CONFIGURATION
This system uses the Serial Presence Detect (SPD) method of determining the installed DIMM
configuration. The BIOS communicates with an EEPROM on each DIMM through an I2C-type
bus to obtain data on the following DIMM parameters:
♦ Presence
♦ Size
♦ Type
♦ Timing/CAS latency
NOTE: Refer to Chapter 3, “Processor/Memory Subsystem” for the SPD format an d DIMM
data specific to this system.
The BIOS performs memory detection and configuration with the following steps:
1. Set Memory Buffer Strength – The memory control ler must be configured for correct buffer
drive strength. The BIOS provides this function by reading the number of module banks,
ECC enable/disable status, and SDRAM width data from the DIMMs and transferring that
data to the memory controller. SPD bytes checked: 5, 11, 13
2. Determine DIMM Presence/Type – The BIOS check s each memory socket for DIMM
presence. If pres ent, the DIMM type and CAS latency is determi ned. SPD bytes checked: 2,
9, 10, 18, 23, 24.
Check Sequence:
a. SPD byte 2 is read for all slots first. A failed read or returned value of other than 02h
(EDO) or 04h (SDRAM) results in the slot marked as empty. If mixed types are detected
then only SDRAMs ar e used (see chapter 3 for d etails).
b. SPD byte 18 is read for maximum CAS latency, followed by reads of bytes 9 and 10 for
bus speed compatibility. A DIMM detected as too-slow results in an error.
c. If the DIMM can handle the memory bus speed at maximum CAS latency then bytes 23
and 24 are checked to see if the DIMM can work maximum CAS latency minus 1. Once
all slots are ch ecked, the greatest CAS latency (2 or 3) is u sed. A DIMM detected as
incompatible will result in a bit in CMOS being set and the Num Lock LED on the
keyboard will blink for a short time. Depending on the progress of the BIOS routine a
POST message may be displayed before the system locks up.
3. Initialize SDRAM – If SDRAM are installed then each row containing SDRAM will be
initialized. This step includes pre-charging all banks, sending a CAS-before-RAS command,
sending a Mode-Register-Set-Enable command, reading DIMM location/CAS latency data,
and sending a Normal Op command.
4. Memory Sizing – The SPD bytes 3, 4, and 17 are check ed for number of row and colu mn
addresses and (for SDRAM) the number of internal banks.
5. Memory Timing – For SDRAM, the memory controller requires the RAS pre-charge time
and the RAS-to-CAS delay time. SPD bytes checked: 27and 29.