Compaq iPAQ Internet Device TABLE OF CONTENTS

Technical Reference Guide
Compaq iPAQ Family of Internet Devices
First Edition - March 2000
iii
TABLE OF CONTENTS
CHAPTER 1 INTRODUCTION.............................................................................................................
1.1 ABOUT THIS GUIDE........................................................................................................... 1-1
1.1.1 USING THIS GUIDE..................................................................................................... 1-1
1.1.2 ADDITIONAL INFORMATION SOURCES.................................................................. 1-1
MODEL NUMBERING CONVENTION...........................................................................................1-1
1.3 NOTATIONAL CONVENTIONS.......................................................................................... 1-2
1.3.1 VALUES........................................................................................................................1-2
1.3.2 RANGES........................................................................................................................ 1-2
1.3.3 SIGNAL LABELS.......................................................................................................... 1-2
1.3.4 REGISTER NOTATION AND USAGE ......................................................................... 1-2
1.3.5 BIT NOTATION............................................................................................................1-2
1.4 COMMON ACRONYMS AND ABBREVIATI ONS.............................................................. 1-3
CHAPTER 2 SYSTEM OVERVIEW.....................................................................................................
2.1 INTRODUCTION.................................................................................................................. 2-1
2.2 FEATURES AND OPTIONS .................................................................................................2-2
2.2.1 STANDARD FEATURES ..............................................................................................2-2
2.2.2 OPTIONS.......................................................................................................................2-3
2.3 MECHANICAL DESIGN...................................................................................................... 2-4
2.3.1 CABINET LAYOUTS.................................................................................................... 2-4
2.3.2 CHASSIS LAYOUT....................................................................................................... 2-6
2.3.3 SYSTEM BOARD LAYOUTS .......................................................................................2-7
2.4 SYSTEM ARCHITECTURE..................................................................................................2-8
2.4.1 PROCESSORS.............................................................................................................2-10
2.4.2 CHIPSET..................................................................................................................... 2-12
2.4.3 SUPPORT COMPONENTS..........................................................................................2-13
2.4.4 SYSTEM MEMORY....................................................................................................2-13
2.4.5 MASS STORAGE........................................................................................................ 2-14
2.4.6 SERIAL AND PARALLEL INTERFACES .................................................................. 2-14
2.4.7 UNIVERSAL SERIAL BUS INTERFACE................................................................... 2-14
2.4.8 GRAPHICS SUBSYSTEM...........................................................................................2-14
2.4.9 AUDIO SUBSYSTEM................................................................................................. 2-15
2.5 SPECIFICATIONS..............................................................................................................2-15
CHAPTER 3 PROCESSOR/MEMORY SUBSYSTEM........................................................................
3.1 INTRODUCTION.................................................................................................................. 3-1
3.2 PROCESSOR.........................................................................................................................3-2
3.2.1 CELERON PROCESSOR...............................................................................................3-2
3.2.2 PENTIUM III PROCESSOR...........................................................................................3-3
3.2.3 PROCESSOR UPGRADING..........................................................................................3-4
3.3 MEMORY SUBSYSTEM...................................................................................................... 3-5
3.4 SUBSYSTEM CONFIGURATION........................................................................................ 3-8