Compaq iPAQ Internet Device LIST OF FIGURES

Technical Reference Guide
Compaq iPAQ Family of Internet Devices
First Edition –- March 2000
viii
LIST OF FIGURES
FIGURE 2–1. COMPAQ IPAQ INTERNET DEVICE WITH MONITOR.............................................................2-1
FIGURE 2–2. COMPAQ IPAQ INTERNET DEVICE, FRONT VIEW................................................................2-4
FIGURE 2–3. COMPAQ IPAQ INTERNET DEVICE, REAR VIEWS................................................................2-5
FIGURE 2–4. COMPAQ IPAQ INTERNET DEVICE CHASSIS LAYOUT, RIDE SIDE VIEW................................2-6
FIGURE 2–5. COMPAQ IPAQ SYSTEM BOARD LAYOUTS......................................................................... 2-7
FIGURE 2–6. COMPAQ IPAQ ARCHITECTURE, BLOCK DIAGRAM.............................................................. 2-9
FIGURE 2–7. PROCESSOR ASSEMBLY AND MOUNTING.......................................................................... 2-11
FIGURE 3–1. PROCESSOR/MEMORY SUBSYSTEM ARCHITECTURE............................................................ 3-1
FIGURE 3–2. CELERON PROCESSOR INTERNAL ARCHITECTURE...............................................................3-2
FIGURE 3–3. PENTIUM III PROCESSOR INTERNAL ARCHITECTURE...........................................................3-3
FIGURE 3–4. SYSTEM MEMORY MAP.....................................................................................................3-7
FIGURE 4-1. PCI BUS DEVICES AND FUNCTIONS..................................................................................... 4-2
FIGURE 4-2. TYPE 0 CONFIGURATION CYCLE.........................................................................................4-4
FIGURE 4-3. PCI CONFIGURATION SPACE MAP...................................................................................... 4-5
FIGURE 4-4. AGP 1X DATA TRANSFER (PEAK TRANSFER RATE: 266 MB/S)...........................................4-9
FIGURE 4-5. AGP 2X DATA TRANSFER (PEAK TRANSFER RATE: 532 MB/S).........................................4-10
FIGURE 4-6. MASKABLE INTERRUPT PROCESSING, BLOCK DIAGRAM.....................................................4-12
FIGURE 4-7. CONFIGURATION MEMORY MAP.......................................................................................4-17
FIGURE 5-1. 40-PIN PRIMARY IDE CONNECTOR (ON SYSTEM BOARD)......................................................5-3
FIGURE 5-2. 50-PIN SECONDARY IDE CONNECTOR (ON SYSTEM AND DAUGHTER BOARDS)....................... 5-4
FIGURE 5-3. SERIAL INTERFACE CONNECTOR (MALE DB-9 AS VIEWED FROM REAR OF CHASSI S) ............... 5-5
FIGURE 5-4. SERIAL INTERFACE HEADER (ON LEGACY-FREE SYSTEM BOARD)........................................... 5-6
FIGURE 5-5. PARALLEL INTERFACE CONNECTOR (FEMALE DB-25 AS VIEWED FROM R EAR OF CHASSIS).... 5-14
FIGURE 5-6. 8042-TO-KEYBOARD TRANSMISSION OF CODE EDH, TIMING DIAGRAM............................. 5-15
FIGURE 5-7. KEYBOARD OR POINTING DEVICE INTERFACE CONNECTOR................................................ 5-21
FIGURE 5-8. USB I/F, BLOCK DIAGRAM............................................................................................... 5-22
FIGURE 5-9. USB PACKET FORMATS.................................................................................................... 5-23
FIGURE 5-10. UNIVERSAL SERIAL BUS CONNECTOR.............................................................................. 5-25
FIGURE 5-11. AUDIO SUBSYSTEM FUNCTIONAL BLOCK DIAGRAM......................................................... 5-27
FIGURE 5-12. AC’97 LINK BUS PROTOCOL.......................................................................................... 5-28
FIGURE 5-13. AD1881 AUDIO CODEC FUNCTIONAL BLOCK DIAGRAM...................................................5-29
FIGURE 5-14. 10/100 TX NETWORK INTERFACE CONTROLLER BLOCK DIAGRAM...................................5-32
FIGURE 5-15. ETHERNET TPE CONNECTOR (RJ-45, VIEWED FROM CARD EDGE)..................................... 5-36
FIGURE 6-1. GRAPHICS SUBSYSTEM BLOCK DIAGRAM............................................................................ 6-2
FIGURE 6-2. 82810E/DC-100 INTEGRATED GRAPHICS CONTROLLER....................................................... 6-3
FIGURE 7–1. POWER DISTRIBUTION AND CONTROL, BLOCK DIAGRAM.....................................................7-1
FIGURE 7–2. POWER CABLE DIAGRAM.................................................................................................. 7-4
FIGURE 7–3. SIGNAL DISTRIBUTION DIAGRAM.......................................................................................7-5
FIGURE 7–4. HEADER PINOUTS............................................................................................................. 7-6
FIGURE B–1. ASCII CHARACTER SET................................................................................................... B-1