Chapter 4 System Support
Compaq iPAQ Family of Internet Devices
First Edition - March 2000
4-8
4.3 AGP BUS OVERVIEW
NOTE: This section provides a brief overview of AGP bus operation. For a detailed
description of AGP bus operations refer to the AGP Interface Specification available at
the following AGP forum web site: http://www.ag pforum. org/ind ex.htm
The Accelerated G raphics Port (AGP) bus is specifically designed as an economical yet hi gh-
performance in terface for graph ics adapters, especia lly those designed for 3D oper ations. The
AGP interface is d esigned to give graph ics adapters dedica ted pipelined access t o system memory
for the purpose of off-loading texturing, z-buffering, and alpha blending used in 3D graphics
operations. By off-loading a large portion of 3D data to system memory the AGP graphics
adapter only requires enough memory for frame buffer (display image) refreshing.
As this system is designed for simplicity of system management, the AGP bus is not available
for expansion purposes.
4.3.1 BUS TRANSACTIONS
The operation of the AGP bus is based on the 66-MHz PCI specification but includes additional
mechanisms to increase bandwidth. During the configuration phase the AGP bus acts in
accordance with PCI protocol. Once graphics data handling operation is initiated, AGP-defined
protocols take effect. The AGP graphics adapter acts generally as the AGP master, but can also
behave as a “PCI” target during fast writes from the GMCH or MCH.
Key differences between the AG P interface and th e PCI interface ar e as follows:
♦ Address phase an d associated data t ransfer phase ar e disconnected tra nsactions. Addr essing
and data transferring occur as contiguous actions on the PCI bus. On the AGP bus a request
for data and the transfer of data may be separated by other operations.
♦ Commands on th e AGP bus specify system memory accesses only. Unl ike the PCI bus,
commands involving I/O and configuration are not required or allowed. The system memory
address space used in AGP operations is the same linear space used by PCI memory space
commands, but i s further specified by the g raphics addres s re-mapping ta ble (GART) of the
north bridge component.
♦ Data transactions on the AGP bus involve eight bytes or multiples of eight bytes. The AGP
memory addressing protocol uses 8-byte boundaries as opposed to PCI’s 4-byte boundari es. If
a transfer of less than eight bytes is needed, the remaining bytes are filled with arbitrary data
that is discarded by the target.
♦ Pipelined requests are defined by length or size on the AGP bus. The PCI bus defines
transfer lengths with the FRAME- signal.
There are two basic types of transactions on the AGP bus: data requests (addressing) and data
transfers. These actions are sep arate from each oth er.