Chapter 4 System Support
Compaq iPAQ Family of Internet Devices
First Edition - March 2000
4-6
4.2.2 PCI INTERRUPT MAPPING
The PCI bus provides for four interrupt signals; INTA-, INTB-, INTC-, and INTD-. These
signals m ay be generated by on-board PCI de vices or by devices in stalled in t he PCI slots. In
order to minimize latency, INTx- signal routing from the interrupt controller of the ICH to PCI
slots/device s is distribu ted evenly as sh own below:
Intr.
Cntlr.
AGP
Cntlr.
Audio
Cntlr.
NIC I/F USB I/F
INTA- INTA- -- -- --
INTB- INTB- INTB- -- --
INTC------- --
INTD- -- -- INTA- INTD-
NOTE:
Interrupts generated by PCI devices can be c onfigured to share the standard AT (IRQn) interrupt lines.
Two devices that share a single PCI interrupt mus t also share the corresponding AT interrupt.
4.2.3 PCI POWER MANAGEMENT SUPPORT
This system complies with the PCI Power Management Interface Specification (rev 1.0). The PCI
Power Management Enable (PME-) signal is supported by the 810 and 820 chipsets and allows
compliant PCI and AGP peripherals to initiate the power management routine.
4.2.4 PCI SUB-BUSSES
The 810e chipset implements two data busses that supplement the PCI bus:
Hub Link Bu s
LPC Bus
4.2.4.1 Hub Link Bus
The 810e chipset implements a Hub Link bus between the GMCH and the ICH. The Hub Link
bus handles transactions at a 66-MHz rate using PCI-type protocol. This bus is transparent to
software and not accessible for expansion purposes.
4.2.4.2 LPC Bus
The 82801 ICH implements a Low Pin Count (LPC) bus for handling transactions to and from
the 47B277 Super I/O Controller as well as the 82802 FWH. The LPC bus transfers data a nibble
(4 bits) at a time at a 33-MHz rate. This bus is transparent to software and not accessible for
expansion purposes.