Technical Reference Guide
Compaq iPAQ Family of Internet Devices
First Edition - March 2000
5-1
Chapter 5INPUT/OUTPUT I NTERFACES

5. Chapter 5 INPUT/OUTPUT INTERFACES

5.1 INTRODUCTION

This chapter describes the standard (i.e., system board) interfaces that provide input and output
(I/O) porting of data and specifically discusses interfaces that are controlled through I/O-mapped
registers. The following I/O interfaces are covered in this chapter:
Enhanced IDE interface (5.2) pag e 5-1
Diskette drive interface (5.3) page 5-4
Serial interfaces (5.4) page 5-5
Parallel interface (5.5) page 5-8
Keyboard/pointing device interface (5.6) page 5-15
Universal serial bus interface (5.7) page 5-22
Audio subsystem (5.8) page 5-26
Network support (5.9) page 5-32

5.2 ENHANCED IDE INTERFACE

The enhanced IDE (EIDE) interface consists of primary and secondary controllers integrated into
the 82801 ICH component of the chipset. The system board includes two IDE connectors, a 40-
pin connector that is associated with the primary controller that controls the internal hard drive
and a 50-pin connector associated with the secondary cont roller that con trols the device in t he
Multibay. Each controller can be configured independently for the following modes of operation:
Programmed I/O (PIO) mode – CPU controls drive transactions through standard I/O
mapped registers of the IDE drive.
8237 DMA mode – CPU offloads drive transactions using DMA protocol with transfer rates
up to 16 MB/s.
Ultra ATA/33 and /66 modes – Preferred bus mastering source-synchronous protocol
providing transfer rates of 33 and 66 MB/s respectively.
NOTE: Although th e EIDE interface can electrically han dle four EIDE devices, th e
form factor of the unit chassis allows only two devices to be installed.

5.2.1 IDE PROGRAMMING

The IDE interface is configured as a PCI device during POST and controlled through I/O-
mapped registers at runtime.