Connect Tech FreeForm/PCI-104 User Manual
Revision 0.02 11
PCI-104 Header (P1)
Refer to PCI-104 specifications.
Note: P1 must be connected to a PCI-104 stack supplying both 3.3V and 5V.
JTAG Programming Header (P2)
Use P2 to configure the FPGA via JTAG. Refer to FPGA Configuration for more information.
Power pins are for voltage reference only; they do not provide power to the configuration
circuitry.
Note that the FPGA can always be programmed via JTAG, regardless of the J1 configuration
setting.
Table 4: JTAG Programming Header Pinout (P2)
Pin Signal Direction
1 TRST Input
2 TMS Input
3 TDI Input
4 TDO Output
5 TCK Input
6 GND Reference
7 3.3V Reference
P2 JTAG
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SPI Flash Programming Header (P3)
P3 may be used to directly program the SPI flash, providing that J1 is set correctly to the tri-state
FPGA position. The power pins are for voltage reference only. They do not provide power to the
configuration circuitry.
Table 5: SPI Flash Programming Header Pinout (P3)
Pin Signal Direction
1 SPI_CSN Input
2 SPI_MOSI Input
3 SPI_MISO Output
4 SPI_CLK Input
5 GND Reference
6 3.3V Reference
1
P3
SPI Flash
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