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Reference Design
The top level reference design contains a generic parameter which will correctly configure the FPGA for Revision B or Revision C. A separate constraint file UCF is created for Revision B and Revision C, which need to be added to the ISE project manually.
| Revision B |
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Local Clock Generation |
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Pin | Signal Name | Local clock generated in | |||
FPGA and forwarded to PLX | |||||
Y21 | lb_lclkfb | ||||
bridge. Clock feedback to | |||||
A20 | lb_lclko_loop | FPGA via pin Y21. | |||
B21 | lb_lclko_plx |
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DDR2 Pinout |
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Pin | Signal Name |
| Pin | Signal Name | |
AA9 | ddr2_a<0> |
| AD21 | ddr2_dq<0> | |
Y8 | ddr2_a<1> |
| AD15 | ddr2_dq<1> | |
AD8 | ddr2_a<2> |
| AC21 | ddr2_dq<2> | |
Y7 | ddr2_a<3> |
| AD14 | ddr2_dq<3> | |
AB9 | ddr2_a<4> |
| AE13 | ddr2_dq<4> | |
W9 | ddr2_a<5> |
| AE22 | ddr2_dq<5> | |
AC8 | ddr2_a<6> |
| AD16 | ddr2_dq<6> | |
AD6 | ddr2_a<7> |
| AE17 | ddr2_dq<7> | |
AA8 | ddr2_a<8> |
| AF10 | ddr2_dq<8> | |
V8 | ddr2_a<9> |
| AE5 | ddr2_dq<9> | |
AC7 | ddr2_a<10> |
| AE12 | ddr2_dq<10> | |
AB7 | ddr2_a<11> |
| AF3 | ddr2_dq<11> | |
AB6 | ddr2_a<12> |
| AF4 | ddr2_dq<12> | |
AC9 | ddr2_a<13> |
| AF12 | ddr2_dq<13> | |
AE7 | ddr2_ba<0> |
| AF5 | ddr2_dq<14> | |
AA5 | ddr2_ba<1> |
| AF9 | ddr2_dq<15> | |
V9 | ddr2_ba<2> |
| AD24 | ddr2_dq<16> | |
AE8 | ddr2_cas_n |
| AE25 | ddr2_dq<17> | |
AE11 | ddr2_ck<0> |
| AC26 | ddr2_dq<18> | |
AD11 | ddr2_ck_n<0> |
| AC23 | ddr2_dq<19> | |
AD18 | ddr2_cke<0> |
| AB22 | ddr2_dq<20> | |
AC22 | ddr2_cs_n<0> |
| AC24 | ddr2_dq<21> | |
AE16 | ddr2_dm<0> |
| AE26 | ddr2_dq<22> | |
AE6 | ddr2_dm<1> |
| AD26 | ddr2_dq<23> | |
AD25 | ddr2_dm<2> |
| AD23 | ddr2_dq<24> | |
AE18 | ddr2_dm<3> |
| AE15 | ddr2_dq<25> | |
AD19 | ddr2_dqs<0> |
| AF24 | ddr2_dq<26> | |
AF7 | ddr2_dqs<1> |
| AF13 | ddr2_dq<27> | |
AF20 | ddr2_dqs<2> |
| AF14 | ddr2_dq<28> | |
AF22 | ddr2_dqs<3> |
| AF25 | ddr2_dq<29> | |
AD20 | ddr2_dqs_n<0> |
| AF15 | ddr2_dq<30> | |
AF8 | ddr2_dqs_n<1> |
| AF23 | ddr2_dq<31> | |
AE20 | ddr2_dqs_n<2> |
| AD13 | ddr2_odt<0> | |
AE21 | ddr2_dqs_n<3> |
| AA7 | ddr2_ras_n | |
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| AB5 | ddr2_we_n | |
| Revision C |
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Pin | Signal Name | Dedicated oscillator | ||
generates local bus clock. | ||||
Y21 | lb_lclkfb | |||
Clock is driven to FPGA on | ||||
A20 |
| pin Y21, which drives an | ||
B21 |
| internal global clock net. | ||
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Pin | Signal Name | Pin | Signal Name | |
AA9 | ddr2_a<0> | AC21 | ddr2_dq<0> | |
Y8 | ddr2_a<1> | AD15 | ddr2_dq<1> | |
AD8 | ddr2_a<2> | AC23 | ddr2_dq<2> | |
Y7 | ddr2_a<3> | AE13 | ddr2_dq<3> | |
AB9 | ddr2_a<4> | AD14 | ddr2_dq<4> | |
W9 | ddr2_a<5> | AE22 | ddr2_dq<5> | |
AE8 | ddr2_a<6> | AD16 | ddr2_dq<6> | |
AD6 | ddr2_a<7> | AD21 | ddr2_dq<7> | |
AA8 | ddr2_a<8> | AF10 | ddr2_dq<8> | |
V8 | ddr2_a<9> | AE5 | ddr2_dq<9> | |
AC7 | ddr2_a<10> | AE12 | ddr2_dq<10> | |
AB7 | ddr2_a<11> | AF3 | ddr2_dq<11> | |
AB6 | ddr2_a<12> | AF4 | ddr2_dq<12> | |
AD10 | ddr2_a<13> | AF12 | ddr2_dq<13> | |
AE7 | ddr2_ba<0> | AF5 | ddr2_dq<14> | |
AA5 | ddr2_ba<1> | AF9 | ddr2_dq<15> | |
V9 | ddr2_ba<2> | AC26 | ddr2_dq<16> | |
AC9 | ddr2_cas_n | AE26 | ddr2_dq<17> | |
AE11 | ddr2_ck<0> | AC24 | ddr2_dq<18> | |
AD11 | ddr2_ck_n<0> | AD24 | ddr2_dq<19> | |
AC8 | ddr2_cke<0> | AE25 | ddr2_dq<20> | |
W8 | ddr2_cs_n<0> | AB22 | ddr2_dq<21> | |
AE16 | ddr2_dm<0> | AD26 | ddr2_dq<22> | |
AE6 | ddr2_dm<1> | AD25 | ddr2_dq<23> | |
AE17 | ddr2_dm<2> | AD23 | Ddr2_dq<24> | |
AE18 | ddr2_dm<3> | AE15 | Ddr2_dq<25> | |
AD19 | ddr2_dqs<0> | AF25 | ddr2_dq<26> | |
AF7 | ddr2_dqs<1> | AF13 | ddr2_dq<27> | |
AF20 | ddr2_dqs<2> | AF14 | ddr2_dq<28> | |
AF22 | ddr2_dqs<3> | AF24 | ddr2_dq<29> | |
AD20 | ddr2_dqs_n<0> | AF15 | ddr2_dq<30> | |
AF8 | ddr2_dqs_n<1> | AF23 | ddr2_dq<31> | |
AE20 | ddr2_dqs_n<2> | AD9 | ddr2_odt<0> | |
AE21 | ddr2_dqs_n<3> | AA7 | ddr2_ras_n | |
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| AB5 | ddr2_we_n | |
Revision 0.02 | 37 |
