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Cypress CY14E102N manual Switching Waveforms, SRAM Read Cycle #1 Address Controlled12, 13, Advance

Models: CY14E102N CY14E102L

1 21

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		ADVANCE	CY14E102L, CY14E102N

Switching Waveforms

Figure 5. SRAM Read Cycle #1: Address Controlled[12, 13, 23]

ADDRESS

tRC

tAA

tOHA

DQ (DATA OUT)

DATA VALID

Figure 6. SRAM Read Cycle #2: CE and OE Controlled[12, 23, 25]

ADDRESS

BHE , BLE

DQ (DATA OUT)

ICC

tRC

tACE

tLZCE

tDOE

tLZOE

tDBE

tLZBE

tPU ACTIVE

STANDBY

tPD

tHZCE

tHZOE

tHZCE tHZBE

DATA VALID

Notes

23.HSB must remain HIGH during READ and WRITE cycles.

24.CE or WE must be >VIH during address transitions.

25.BHE and BLE are applicable for x16 configuration only.

Document Number: 001-45755 Rev. *A

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Cypress Switching Waveforms, SRAM Read Cycle #1 Address Controlled12, 13, Advance, CY14E102L, CY14E102N, + Feedback

Contents

CY14E102L, CY14E102N FeaturesLogic Block Diagram ADVANCENot to Scale Figure 1. Pin Diagram - 48 FBGA Top ViewFigure 2. Pin Diagram - 44 TSOP II Top View PinoutsByte Low Enable, Active LOW. Controls DQ7 - DQ0 Figure 3. Pin Diagram - 54 TSOP II Top ViewOutput Enable, Active LOW. The active LOW Byte High Enable, Active LOW. Controls DQ15 - DQ8AutoStore Operation Device OperationSRAM Read SRAM WriteSoftware RECALL Hardware RECALL Power UpPower Software STORETable 1. Mode Selection continued Preventing AutoStoreData Protection Noise ConsiderationsRange DC Electrical CharacteristicsMaximum Ratings Operating RangeAC Test Conditions CapacitanceThermal Resistance AC Test Loads20 ns AC Switching CharacteristicsParameters 15 nsCY14E102L/CY14E102N AutoStore and Power Up RECALLSoftware Controlled STORE and RECALL Cycle Hardware STORE CycleADVANCE Switching WaveformsFigure 5. SRAM Read Cycle #1 Address Controlled12, 13 Figure 6. SRAM Read Cycle #2 CE and OE Controlled12, 23CY14E102L, CY14E102N Figure 8. SRAM Write Cycle #2 CE Controlled13, 21, 22Switching Waveforms continued ADVANCEPOWER-UP RECALL Switching Waveforms continuedFigure 9. AutoStore or Power Up RECALL26 Figure 10. CE Controlled Software STORE/RECALL Cycle19Switching Waveforms continued Figure 11. OE Controlled Software STORE/RECALL Cycle19Figure 12. Hardware STORE Cycle22 Figure 13. Soft Sequence Processing20Ordering Code DiagramOrdering Information SpeedCY14E102L, CY14E102N Ordering Information continuedDiagram ADVANCECY14E102L, CY14E102N Part Numbering NomenclatureCY 14 E 102 L - ZS P 15 X C T ADVANCECY14E102L, CY14E102N Package DiagramsFigure 14. 44-Pin TSOP ADVANCECY14E102L, CY14E102N Package Diagrams continuedFigure 15. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm ADVANCECY14E102L, CY14E102N Figure 16. 54-Pin TSOPPackage Diagrams continued ADVANCEWorldwide Sales and Design Support Sales, Solutions, and Legal InformationPSoC Solutions Document History Page