Switching Waveforms

Figure 5. SRAM Read Cycle #1: Address Controlled[12, 13, 23]

ADDRESS

tRC

tAA

tOHA

DQ (DATA OUT)

DATA VALID

ADDRESS

BHE , BLE

DQ (DATA OUT)

ICC

tRC

tACE

tLZCE

tDOE

tLZOE

tDBE

tLZBE

tPU ACTIVE

STANDBY

tPD

tHZCE

tHZOE

tHZCE tHZBE

DATA VALID

Notes

23.HSB must remain HIGH during READ and WRITE cycles.

24.CE or WE must be >VIH during address transitions.

25.BHE and BLE are applicable for x16 configuration only.

Document Number: 001-45755 Rev. *A

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Contents

Cypress Semiconductor Corporation 198 Champion Court FeaturesLogic Block Diagram Functional Description Not to Scale PinoutsX16 Pin Definitions AutoStore Operation Device OperationSram Read Sram Write Software Store Hardware Recall Power UpMode Selection A15 A0 Mode Power Noise Considerations Mode Selection A15 A0 PowerPreventing AutoStore Data Protection Range DC Electrical CharacteristicsMaximum Ratings Operating Range AC Test Conditions CapacitanceThermal Resistance AC Test Loads Sram Write Cycle AC Switching CharacteristicsMin Max Parameters Sram Read Cycle Hardware Store Cycle AutoStore and Power Up RecallSoftware Controlled Store and Recall Cycle Switching Waveforms Switching Waveforms AutoStore or Power Up RECALL26 Α α Ordering Information CY14E102L-BA25XIT CY14E102L-ZS25XCTCY14E102L-ZS25XIT CY14E102N-BA25XCT Nvsram Part Numbering NomenclatureCY 14 E 102 L ZS P 15 X C T ZS Tsop Pin Tsop Package Diagrams Ball Fbga 6 mm x 10 mm x 1.2 mm 51-85160 Orig. Submission Description of Change Sales, Solutions, and Legal InformationDocument History