Contents
Logic Block Diagram
Features
ADVANCE
CY14E102L, CY14E102N
Figure 2. Pin Diagram - 44 TSOP II Top View
Figure 1. Pin Diagram - 48 FBGA Top View
Pinouts
Not to Scale
Output Enable, Active LOW. The active LOW
Figure 3. Pin Diagram - 54 TSOP II Top View
Byte High Enable, Active LOW. Controls DQ15 - DQ8
Byte Low Enable, Active LOW. Controls DQ7 - DQ0
SRAM Read
Device Operation
SRAM Write
AutoStore Operation
Power
Hardware RECALL Power Up
Software STORE
Software RECALL
Data Protection
Preventing AutoStore
Noise Considerations
Table 1. Mode Selection continued
Maximum Ratings
DC Electrical Characteristics
Operating Range
Range
Thermal Resistance
Capacitance
AC Test Loads
AC Test Conditions
Parameters
AC Switching Characteristics
15 ns
20 ns
Software Controlled STORE and RECALL Cycle
AutoStore and Power Up RECALL
Hardware STORE Cycle
CY14E102L/CY14E102N
Figure 5. SRAM Read Cycle #1 Address Controlled12, 13
Switching Waveforms
Figure 6. SRAM Read Cycle #2 CE and OE Controlled12, 23
ADVANCE
Switching Waveforms continued
Figure 8. SRAM Write Cycle #2 CE Controlled13, 21, 22
ADVANCE
CY14E102L, CY14E102N
Figure 9. AutoStore or Power Up RECALL26
Switching Waveforms continued
Figure 10. CE Controlled Software STORE/RECALL Cycle19
POWER-UP RECALL
Figure 12. Hardware STORE Cycle22
Figure 11. OE Controlled Software STORE/RECALL Cycle19
Figure 13. Soft Sequence Processing20
Switching Waveforms continued
Ordering Information
Diagram
Speed
Ordering Code
Diagram
Ordering Information continued
ADVANCE
CY14E102L, CY14E102N
CY 14 E 102 L - ZS P 15 X C T
Part Numbering Nomenclature
ADVANCE
CY14E102L, CY14E102N
Figure 14. 44-Pin TSOP
Package Diagrams
ADVANCE
CY14E102L, CY14E102N
Figure 15. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm
Package Diagrams continued
ADVANCE
CY14E102L, CY14E102N
Package Diagrams continued
Figure 16. 54-Pin TSOP
ADVANCE
CY14E102L, CY14E102N
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