Cypress CY14E102L Pinouts, Not to Scale, Pin Diagram - 48 FBGA Top View, Advance, + Feedback

ADVANCE CY14E102L, CY14E102N

Pinouts

	Figure 1. Pin Diagram - 48 FBGA (Top View)
(x8)	(x16)
(Not to Scale)	(Not to Scale)

1	2	3	4	5	6
NC	OE	A0	A1	A2	NC	A
NC	NC	A3	A4	CE	NC	B
DQ0	NC	A5	A6	NC	DQ4	C
VSS	DQ1	A17	A7	DQ5	VCC	D
VCC	DQ2	VCAP	A16	DQ6	VSS	E
DQ3	NC	A14	A15	NC	DQ7	F
[4]	HSB	A12	A13	WE	NC	G
NC
[2]	A8	A9	A10	A11	NC[3]	H
NC

1	2	3	4	5	6
BLE	OE	A0	A1	A2	NC	A
DQ8	BHE	A	A	CE	DQ0	B
		3	4
DQ9 DQ10		A5	A6	DQ1	DQ2	C
VSS	DQ11	[2]	A7	DQ3	VCC	D
		NC
VCC DQ12 VCAP			A16	DQ4	VSS	E
DQ14 DQ13		A14	A15	DQ5	DQ6	F
DQ15 HSB		A12	A13	WE	DQ7	G
[3]	A8	A9	A10	A11	[4]	H
NC					NC

Figure 2. Pin Diagram - 44 TSOP II (Top View)

NC		1
				44			HSB
[4]
NC		2		43			NC[3]
	A0	3		42			NC
	A1	4		41			NC[2]
	A2	5		40			A17
	A3	6		39			A
	A4	7		38		16
							A
		8			15
	CE			37			OE
DQ0		9	(x8)	36			DQ7
DQ1		10		35			DQ6

	VCC	11	(Not to Scale)	34	VSS
VSS		12		33	VCC
DQ2		13		32	DQ5
DQ3		14		31	DQ4
		15
	WE			30	VCAP
	A5	16
				29	A14
	A6	17		28	A13
	A7	18		27	A12
	A8	19		26	A11
	A9	20		25	A10
NC		21		24	NC
NC		22		23	NC

		A0	1
		A1	2
		A2	3
		A3	4
		A4	5
		CE	6
DQ0			7
DQ1			8
DQ2			9	(x16)
DQ3			10
VCC			11	(Not to Scale)
VSS			12
DQ4			13
DQ5			14
DQ6			15
DQ7			16
			17
	WE
		A5	18
		A6	19
		A7	20
		A8	21
		A9	22

44 NC[2]

43 A16

42 A15

41 OE

40 BHE

39 BLE

38 DQ15

37 DQ14

36 DQ13

35 DQ12

34 VSS

33 VCC

32 DQ11

31 DQ10

30 DQ9

29 DQ8

28 VCAP

27 A14

26 A13

25 A12

24 A11

23 A10

Notes

2.Address expansion for 4 Mbit. NC pin not connected to die.

3.Address expansion for 8 Mbit. NC pin not connected to die.

4.Address expansion for 16 Mbit. NC pin not connected to die.

Document Number: 001-45755 Rev. *A Page 2 of 21

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