Contents
Features
Logic Block Diagram
ADVANCE
CY14E102L, CY14E102N
Figure 1. Pin Diagram - 48 FBGA Top View
Figure 2. Pin Diagram - 44 TSOP II Top View
Pinouts
Not to Scale
Figure 3. Pin Diagram - 54 TSOP II Top View
Output Enable, Active LOW. The active LOW
Byte High Enable, Active LOW. Controls DQ15 - DQ8
Byte Low Enable, Active LOW. Controls DQ7 - DQ0
Device Operation
SRAM Read
SRAM Write
AutoStore Operation
Hardware RECALL Power Up
Power
Software STORE
Software RECALL
Preventing AutoStore
Data Protection
Noise Considerations
Table 1. Mode Selection continued
DC Electrical Characteristics
Maximum Ratings
Operating Range
Range
Capacitance
Thermal Resistance
AC Test Loads
AC Test Conditions
AC Switching Characteristics
Parameters
15 ns
20 ns
AutoStore and Power Up RECALL
Software Controlled STORE and RECALL Cycle
Hardware STORE Cycle
CY14E102L/CY14E102N
Switching Waveforms
Figure 5. SRAM Read Cycle #1 Address Controlled12, 13
Figure 6. SRAM Read Cycle #2 CE and OE Controlled12, 23
ADVANCE
Figure 8. SRAM Write Cycle #2 CE Controlled13, 21, 22
Switching Waveforms continued
ADVANCE
CY14E102L, CY14E102N
Switching Waveforms continued
Figure 9. AutoStore or Power Up RECALL26
Figure 10. CE Controlled Software STORE/RECALL Cycle19
POWER-UP RECALL
Figure 11. OE Controlled Software STORE/RECALL Cycle19
Figure 12. Hardware STORE Cycle22
Figure 13. Soft Sequence Processing20
Switching Waveforms continued
Diagram
Ordering Information
Speed
Ordering Code
Ordering Information continued
Diagram
ADVANCE
CY14E102L, CY14E102N
Part Numbering Nomenclature
CY 14 E 102 L - ZS P 15 X C T
ADVANCE
CY14E102L, CY14E102N
Package Diagrams
Figure 14. 44-Pin TSOP
ADVANCE
CY14E102L, CY14E102N
Package Diagrams continued
Figure 15. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm
ADVANCE
CY14E102L, CY14E102N
Figure 16. 54-Pin TSOP
Package Diagrams continued
ADVANCE
CY14E102L, CY14E102N
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