Cypress CY14E102L AutoStore and Power Up RECALL, Software Controlled STORE and RECALL Cycle, 15ns

ADVANCE CY14E102L, CY14E102N

AutoStore and Power Up RECALL

Parameters		Description	CY14E102L/CY14E102N		Unit
			Min	Max
t	[16]	Power Up RECALL Duration		20	ms
HRECALL
tSTORE [17]		STORE Cycle Duration		15	ms
VSWITCH		Low Voltage Trigger Level		4.4	V
tVCCRISE		VCC Rise Time	150		μs

Software Controlled STORE and RECALL Cycle

The following table lists the software controlled STORE and RECALL cycle parameters.[18, 19]

Parameters	Description	15ns		20 ns		25ns		45ns		Unit
		Min	Max	Min	Max	Min	Max	Min	Max
tRC	STORE and RECALL Initiation Cycle Time	15		20		25		45		ns
tAS	Address Setup Time	0		0		0		0		ns
tCW	Clock Pulse Width	12		15		20		30		ns
tGHAX	Address Hold Time	1		1		1		1		ns
tRECALL	RECALL Duration		200		200		200		200	μs
tSS [20, 21]	Soft Sequence Processing Time		70		70		70		70	μs

Hardware STORE Cycle

Parameters	Description	CY14E102L/CY14E102N		Unit
		Min	Max
tDELAY [22]	Time allowed to complete SRAM cycle	1	70	μs
tHLHX	Hardware STORE pulse width	15		ns

Notes

16.tHRECALL starts from the time VCC rises above VSWITCH.

17.If an SRAM Write has not taken place since the last nonvolatile cycle, no STORE takes place.

18.The software sequence is clocked with CE controlled or OE controlled reads.

19.The six consecutive addresses must be read in the order listed in the mode selection table. WE must be HIGH during all six consecutive cycles.

20.This is the amount of time it takes to take action on a soft sequence command.Vcc power must remain HIGH to effectively register command.

21.Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.

22.On a hardware STORE initiation, SRAM operation continues to be enabled for time tDELAY to allow read and write cycles to complete.

Document Number: 001-45755 Rev. *A Page 10 of 21

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