Cypress CY7C1320JV18 manual Features, Functional Description, Configurations, Selection Guide

CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Features

■18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)

■300 MHz clock for high bandwidth

■2-word burst for reducing address bus frequency

■Double Data Rate (DDR) interfaces

(data transferred at 600 MHz) at 300 MHz

■Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only

■Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches

■Echo clocks (CQ and CQ) simplify data capture in high-speed systems

■Synchronous internally self-timed writes

■DDR-II operates with 1.5 cycle read latency when the DLL is enabled

■Operates similar to a DDR-I device with 1 cycle read latency in DLL off mode

■1.8V core power supply with HSTL inputs and outputs

■Variable drive HSTL output buffers

■Expanded HSTL output voltage (1.4V–VDD)

■Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)

■Offered in both Pb-free and non Pb-free packages

■JTAG 1149.1 compatible test access port

■Delay Lock Loop (DLL) for accurate data placement

Functional Description

The CY7C1316JV18, CY7C1916JV18, CY7C1318JV18, and CY7C1320JV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1316JV18 and two 9-bit words in the case of CY7C1916JV18 that burst sequentially into or out of the device. The burst counter always starts with a ‘0’ internally in the case of CY7C1316JV18 and CY7C1916JV18. For CY7C1318JV18 and CY7C1320JV18, the burst counter takes in the least significant bit of the external address and bursts two 18-bit words (in the case of CY7C1318JV18) of two 36-bit words (in the case of CY7C1320JV18) sequentially into or out of the device.

Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same physical pins as the data inputs, D) are tightly matched to the two output echo clocks CQ/CQ, eliminating the need to capture data separately from each individual DDR SRAM in the system design. Output data clocks (C/C) enable maximum system clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

Configurations

CY7C1316JV18 – 2M x 8

CY7C1916JV18 – 2M x 9

CY7C1318JV18 – 1M x 18

CY7C1320JV18 – 512K x 36

Selection Guide

	Description		300 MHz	Unit
Maximum Operating Frequency			300	MHz
Maximum Operating Current		x8	610	mA
		x9	615
		x18	655
		x36	730

Cypress Semiconductor Corporation • 198 Champion Court	•	San Jose, CA 95134-1709	•	408-943-2600
Document Number: 001-15271 Rev. *B		Revised March 10, 2008

[+] Feedback