Manuals / Cypress / Computer Equipment / Computer Hardware

Cypress manual Ordering Information, CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18

Models: CY7C1318JV18 CY7C1316JV18 CY7C1916JV18 CY7C1320JV18

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Ordering Information

CY7C1316JV18, CY7C1916JV18

CY7C1318JV18, CY7C1320JV18

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Diagram	Package Type	Range
300	CY7C1316JV18-300BZC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Commercial

	CY7C1916JV18-300BZC

	CY7C1318JV18-300BZC

	CY7C1320JV18-300BZC

	CY7C1316JV18-300BZXC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1916JV18-300BZXC

	CY7C1318JV18-300BZXC

	CY7C1320JV18-300BZXC

	CY7C1316JV18-300BZI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Industrial

	CY7C1916JV18-300BZI

	CY7C1318JV18-300BZI

	CY7C1320JV18-300BZI

	CY7C1316JV18-300BZXI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1916JV18-300BZXI

	CY7C1318JV18-300BZXI

	CY7C1320JV18-300BZXI

Document Number: 001-15271 Rev. *B

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Cypress manual Ordering Information, CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18

Contents

Features ConfigurationsCY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Functional DescriptionLogic Block Diagram CY7C1316JV18 Logic Block Diagram CY7C1916JV18CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 + FeedbackLogic Block Diagram CY7C1318JV18 Logic Block Diagram CY7C1320JV18CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 + FeedbackPin Configuration 165-Ball FBGA 13 x 15 x 1.4 mm PinoutCY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Pin Configuration CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18165-Ball FBGA 13 x 15 x 1.4 mm Pinout CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18Pin Definitions CY7C1318JV18, CY7C1320JV18 Pin Definitions continuedCY7C1316JV18, CY7C1916JV18 Single Clock Mode Functional OverviewRead Operations Write OperationsApplication Example Echo ClocksCY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Write Cycle Descriptions Truth TableBurst Address Table CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Write Cycle DescriptionsWrite Cycle Descriptions Disabling the JTAG Feature Test Access Port-Test ClockTest Mode Select TMS Performing a TAP ResetIDCODE SAMPLE ZSAMPLE/PRELOAD BYPASSTAP Controller State Diagram CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18Page 14 of TAP Controller Block Diagram TAP Electrical CharacteristicsCY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 TAP AC Switching Characteristics TAP Timing and Test ConditionsCY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Identification Register Definitions Scan Register SizesInstruction Codes CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18Boundary Scan Order CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18Power Up Sequence in DDR-II SRAM Power Up WaveformsPower Up Sequence DLL ConstraintsElectrical Characteristics DC Electrical CharacteristicsAC Electrical Characteristics Maximum RatingsCapacitance Thermal ResistanceAC Test Loads and Waveforms CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18Switching Characteristics CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18 ParameterSwitching Waveforms CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18tCQDOH tCQDOrdering Information CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18Package Diagram CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18Figure 4. 165-ball FBGA 13 x 15 x 1.40 mm + FeedbackDocument History Page ISSUECY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Burst Architecture Document Number