Manuals / Cypress / Computer Equipment / Computer Hardware

Cypress CY7C1316JV18, CY7C1320JV18, CY7C1318JV18, CY7C1916JV18 manual Ordering Information

Models: CY7C1318JV18 CY7C1316JV18 CY7C1916JV18 CY7C1320JV18

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CY7C1316JV18, CY7C1916JV18

CY7C1318JV18, CY7C1320JV18

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Diagram	Package Type	Range
300	CY7C1316JV18-300BZC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Commercial

	CY7C1916JV18-300BZC

	CY7C1318JV18-300BZC

	CY7C1320JV18-300BZC

	CY7C1316JV18-300BZXC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1916JV18-300BZXC

	CY7C1318JV18-300BZXC

	CY7C1320JV18-300BZXC

	CY7C1316JV18-300BZI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Industrial

	CY7C1916JV18-300BZI

	CY7C1318JV18-300BZI

	CY7C1320JV18-300BZI

	CY7C1316JV18-300BZXI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1916JV18-300BZXI

	CY7C1318JV18-300BZXI

	CY7C1320JV18-300BZXI

Document Number: 001-15271 Rev. *B

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Cypress CY7C1316JV18, CY7C1320JV18, CY7C1318JV18, CY7C1916JV18 manual Ordering Information

Contents

Features ConfigurationsFunctional Description Selection Guide Logic Block Diagram CY7C1316JV18 Logic Block Diagram CY7C1916JV18Doff CLK Logic Block Diagram CY7C1318JV18 Logic Block Diagram CY7C1320JV18BWS Pin Configuration Ball Fbga 13 x 15 x 1.4 mm PinoutCY7C1316JV18 2M x CY7C1916JV18 2M x CY7C1318JV18 1M x CY7C1320JV18 512K x Pin Definitions Pin Name Pin DescriptionSynchronous Read/Write Input. When Power Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceIs Referenced with Respect to TDO for Jtag Functional Overview Application Example Echo ClocksSRAM#1 ZQ SRAM#2 Write Cycle Descriptions BWS0 BWS1NWS0 NWS1 BWS0 BWS0 BWS1 BWS2 BWS3 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller follows TAP Controller Block Diagram TAP Electrical CharacteristicsTDI TCK TAP AC Switching Characteristics TAP Timing and Test Conditions Identification Register Definitions Scan Register SizesInstruction Codes Boundary Scan Order Bit # Bump ID Power Up Sequence in DDR-II Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsAC Electrical Characteristics Maximum Ratings Capacitance Thermal ResistanceAC Test Loads and Waveforms Parameter Description Test Conditions Max Unit Cypress Consortium Description 300 MHz Unit Parameter Min MaxDLL Timing Switching Waveforms NOPRead NOP Write Read Ordering Information Package Diagram Ball Fbga 13 x 15 x 1.40 mm REV ECN no Issue ORIG. Description of Change Date VKN/KKVTMPVKN/AESA