Contents
Configurations
Features
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Functional Description
Logic Block Diagram CY7C1916JV18
Logic Block Diagram CY7C1316JV18
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
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Logic Block Diagram CY7C1320JV18
Logic Block Diagram CY7C1318JV18
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
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165-Ball FBGA 13 x 15 x 1.4 mm Pinout
Pin Configuration
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Pin Configuration
165-Ball FBGA 13 x 15 x 1.4 mm Pinout
CY7C1318JV18, CY7C1320JV18
CY7C1316JV18, CY7C1916JV18
Pin Definitions
Pin Definitions continued
CY7C1318JV18, CY7C1320JV18
CY7C1316JV18, CY7C1916JV18
Functional Overview
Single Clock Mode
Read Operations
Write Operations
Echo Clocks
Application Example
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Truth Table
Write Cycle Descriptions
Burst Address Table
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Write Cycle Descriptions
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Write Cycle Descriptions
Test Access Port-Test Clock
Disabling the JTAG Feature
Test Mode Select TMS
Performing a TAP Reset
SAMPLE Z
IDCODE
SAMPLE/PRELOAD
BYPASS
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
TAP Controller State Diagram
Page 14 of
TAP Electrical Characteristics
TAP Controller Block Diagram
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
TAP Timing and Test Conditions
TAP AC Switching Characteristics
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Scan Register Sizes
Identification Register Definitions
Instruction Codes
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Boundary Scan Order
Power Up Waveforms
Power Up Sequence in DDR-II SRAM
Power Up Sequence
DLL Constraints
DC Electrical Characteristics
Electrical Characteristics
AC Electrical Characteristics
Maximum Ratings
Thermal Resistance
Capacitance
AC Test Loads and Waveforms
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
CY7C1316JV18, CY7C1916JV18
Switching Characteristics
CY7C1318JV18, CY7C1320JV18
Parameter
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Switching Waveforms
tCQDOH
tCQD
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Ordering Information
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Package Diagram
Figure 4. 165-ball FBGA 13 x 15 x 1.40 mm
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ISSUE
Document History Page
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Burst Architecture Document Number