Cypress CY7C1916JV18 Logic Block Diagram CY7C1318JV18, Logic Block Diagram CY7C1320JV18, Bws

CY7C1316JV18, CY7C1916JV18

CY7C1318JV18, CY7C1320JV18

Logic Block Diagram (CY7C1318JV18)

			A0			Burst
						Logic
	20				19
A(19:0)				A(19:1)		Address
						Register
		LD

K

CLK

K Gen.

DOFF

VREF
		Control
R/W
		Logic
BWS
	[1:0]

	Write	Write
DecodeAdd.Write	Reg	Reg	DecodeAdd.Read
	512Kx18Array	512Kx18Array		Logic	18
				Output	R/W
	Read Data Reg.			Control	C
					C

36							CQ
18		Reg.	Reg.	18			CQ
	18				18
				18		DQ[17:0]
		Reg.

Logic Block Diagram (CY7C1320JV18)

			A0			Burst
						Logic
	19				18
A(18:0)				A(18:1)		Address
						Register
		LD

K

CLK

K Gen.

DOFF

VREF
		Control
R/W
		Logic
BWS
	[3:0]

	Write	Write
DecodeAdd.Write	Reg	Reg	DecodeAdd.Read
	256Kx36Array	256Kx36Array		Logic	36
				Output	R/W
	Read Data Reg.			Control	C
					C

72							CQ
36		Reg.	Reg.	36			CQ
	36				36
				36		DQ[35:0]
		Reg.

Document Number: 001-15271 Rev. *B Page 3 of 26

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