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Cypress Switching Waveforms, CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18, tCQDOH

Models: CY7C1318JV18 CY7C1316JV18 CY7C1916JV18 CY7C1320JV18

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CY7C1316JV18, CY7C1916JV18

CY7C1318JV18, CY7C1320JV18

Switching Waveforms

Figure 3. Read/Write/Deselect Sequence [24, 25, 26]

NOP		READ	READ
1		2	3
K
tKH	tKL	tCYC	tKHKH
K
LD	tSC
	tSC	tHC
R/W

NOP	NOP	WRITE	WRITE	READ
4	5	6	7	8	9	10

A	A0	A1
tSA		tHA

tKHCH tCLZ tCO

tHD

tSD

Q00 Q01 Q10	Q11
tCQDOH
tDOH	tCHZ
tCQD

tHD

tSD

D21

D30

D31

Q41

t KHCH

tKH tKL	tCYC	tKHKH

tCQOH

tCCQO

tCQOH

CQ#

tCCQO	tCQH	tCQHCQH

DON’T CARE

UNDEFINED

Notes

24.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.

25.Outputs are disabled (High-Z) one clock cycle after a NOP.

26.In this example, if address A2 = A1, then data D20 = Q10 and D21 = Q11. Write data is forwarded immediately as read results. This note applies to the whole diagram.

Document Number: 001-15271 Rev. *B

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Cypress manual Switching Waveforms, CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18, tCQDOH, + Feedback

Contents

Functional Description FeaturesConfigurations CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18+ Feedback Logic Block Diagram CY7C1316JV18Logic Block Diagram CY7C1916JV18 CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18+ Feedback Logic Block Diagram CY7C1318JV18Logic Block Diagram CY7C1320JV18 CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Pin Configuration165-Ball FBGA 13 x 15 x 1.4 mm Pinout 165-Ball FBGA 13 x 15 x 1.4 mm Pinout Pin ConfigurationCY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Pin Definitions CY7C1316JV18, CY7C1916JV18CY7C1318JV18, CY7C1320JV18 CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18Pin Definitions continued Write Operations Single Clock ModeFunctional Overview Read OperationsCY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Application ExampleEcho Clocks CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Write Cycle DescriptionsTruth Table Burst Address TableWrite Cycle Descriptions CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18Write Cycle Descriptions Performing a TAP Reset Disabling the JTAG FeatureTest Access Port-Test Clock Test Mode Select TMSBYPASS IDCODESAMPLE Z SAMPLE/PRELOADPage 14 of TAP Controller State DiagramCY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 TAP Controller Block DiagramTAP Electrical Characteristics CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 TAP AC Switching CharacteristicsTAP Timing and Test Conditions CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Identification Register DefinitionsScan Register Sizes Instruction CodesCY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Boundary Scan OrderDLL Constraints Power Up Sequence in DDR-II SRAMPower Up Waveforms Power Up SequenceMaximum Ratings Electrical CharacteristicsDC Electrical Characteristics AC Electrical CharacteristicsCY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 CapacitanceThermal Resistance AC Test Loads and WaveformsParameter Switching CharacteristicsCY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18tCQD Switching WaveformsCY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 tCQDOHCY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Ordering Information+ Feedback Package DiagramCY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 Figure 4. 165-ball FBGA 13 x 15 x 1.40 mmBurst Architecture Document Number Document History PageISSUE CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18