CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Features
Configurations
Functional Description
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Logic Block Diagram CY7C1316JV18
Logic Block Diagram CY7C1916JV18
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CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Logic Block Diagram CY7C1318JV18
Logic Block Diagram CY7C1320JV18
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Pin Configuration
165-Ball FBGA 13 x 15 x 1.4 mm Pinout
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Pin Configuration
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
165-Ball FBGA 13 x 15 x 1.4 mm Pinout
CY7C1316JV18, CY7C1916JV18
CY7C1318JV18, CY7C1320JV18
Pin Definitions
CY7C1318JV18, CY7C1320JV18
Pin Definitions continued
CY7C1316JV18, CY7C1916JV18
Read Operations
Single Clock Mode
Functional Overview
Write Operations
Application Example
Echo Clocks
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Burst Address Table
Write Cycle Descriptions
Truth Table
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Write Cycle Descriptions
Write Cycle Descriptions
Test Mode Select TMS
Disabling the JTAG Feature
Test Access Port-Test Clock
Performing a TAP Reset
SAMPLE/PRELOAD
IDCODE
SAMPLE Z
BYPASS
TAP Controller State Diagram
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Page 14 of
TAP Controller Block Diagram
TAP Electrical Characteristics
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
TAP AC Switching Characteristics
TAP Timing and Test Conditions
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Instruction Codes
Identification Register Definitions
Scan Register Sizes
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Boundary Scan Order
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Power Up Sequence
Power Up Sequence in DDR-II SRAM
Power Up Waveforms
DLL Constraints
AC Electrical Characteristics
Electrical Characteristics
DC Electrical Characteristics
Maximum Ratings
AC Test Loads and Waveforms
Capacitance
Thermal Resistance
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
CY7C1318JV18, CY7C1320JV18
Switching Characteristics
CY7C1316JV18, CY7C1916JV18
Parameter
tCQDOH
Switching Waveforms
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
tCQD
Ordering Information
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Figure 4. 165-ball FBGA 13 x 15 x 1.40 mm
Package Diagram
CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
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CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Document History Page
ISSUE
Burst Architecture Document Number