Cypress CY7C1475BV25, CY7C1471BV25, CY7C1473BV25 manual Scan Register Sizes Register Name Bit Size

CY7C1471BV25

CY7C1473BV25, CY7C1475BV25

Table 8. Identification Register Definitions

Instruction Field	CY7C1471BV25	CY7C1473BV25	CY7C1475BV25	Description
	(2MX36)	(4MX18)	(1MX72)
Revision Number (31:29)	000	000	000	Describes the version number
Device Depth (28:24)	01011	01011	01011	Reserved for internal use
Architecture/Memory Type(23:18)	001001	001001	001001	Defines memory type and architecture
Bus Width/Density(17:12)	100100	010100	110100	Defines width and density
Cypress JEDEC ID Code (11:1)	00000110100	00000110100	00000110100	Allows unique identification of SRAM
				vendor
ID Register Presence Indicator (0)	1	1	1	Indicates the presence of an ID register

Table 9. Scan Register Sizes

Register Name			Bit Size (x36)	Bit Size (x18)	Bit Size (x72)
Instruction		3		3	3
Bypass		1		1	1
ID		32		32	32
Boundary Scan Order – 165FBGA		71		52	-
Boundary Scan Order – 209BGA		-		-	110
Table 10. Identification Codes
Instruction	Code			Description
EXTEST	000		Captures IO ring contents. Places the boundary scan register between TDI and TDO.
			Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.
IDCODE	001		Loads the ID register with the vendor ID code and places the register between TDI
			and TDO. This operation does not affect SRAM operations.
SAMPLE Z	010		Captures IO ring contents. Places the boundary scan register between TDI and TDO.
			Forces all SRAM output drivers to a High-Z state.
RESERVED	011		Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD	100		Captures IO ring contents. Places the boundary scan register between TDI and TDO.
			Does not affect SRAM operation. This instruction does not implement 1149.1 preload
			function and is therefore not 1149.1 compliant.
RESERVED	101		Do Not Use: This instruction is reserved for future use.
RESERVED	110		Do Not Use: This instruction is reserved for future use.
BYPASS	111		Places the bypass register between TDI and TDO. This operation does not affect
			SRAM operation.

Document #: 001-15013 Rev. *E Page 17 of 30

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