Cypress CY7C1473BV25, CY7C1471BV25 manual Switching Characteristics, Output Times, Setup Times

CY7C1471BV25

CY7C1473BV25, CY7C1475BV25

Switching Characteristics

Over the Operating Range. Timing reference level is 1.25V when VDDQ = 2.5V. Test conditions shown in (a) of “AC Test Loads and Waveforms” on page 21 unless otherwise noted.

Parameter	Description	133 MHz		100 MHz		Unit
		Min	Max	Min	Max
tPOWER		1		1		ms
Clock

tCYC	Clock Cycle Time	7.5	10
tCH	Clock HIGH	2.5	3.0
tCL	Clock LOW	2.5	3.0
Output Times

ns

ns

ns

tCDV

tDOH

tCLZ

tCHZ

tOEV

tOELZ

tOEHZ

Data Output Valid After CLK Rise			6.5		8.5	ns
Data Output Hold After CLK Rise		2.5		2.5		ns
Clock to Low-Z [16, 17, 18]		3.0		3.0		ns
Clock to High-Z [16, 17, 18]			3.8		4.5	ns
	LOW to Output Valid		3.0		3.8	ns
OE
	LOW to Output Low-Z [16, 17, 18]	0		0		ns
OE
	HIGH to Output High-Z [16, 17, 18]		3.0		4.0	ns
OE

Setup Times

tAS	Address Setup Before CLK Rise				1.5	1.5
tALS
	ADV/LD			Setup Before CLK Rise	1.5	1.5
tWES				X Setup Before CLK Rise	1.5	1.5
	WE,		BW
tCENS		Setup Before CLK Rise			1.5	1.5
	CEN
tDS	Data Input Setup Before CLK Rise				1.5	1.5
tCES	Chip Enable Setup Before CLK Rise				1.5	1.5
Hold Times

ns

ns

ns

ns

ns

ns

tAH

tALH

tWEH

tCENH

tDH

tCEH

Address Hold After CLK Rise				0.5	0.5
			Hold After CLK Rise	0.5	0.5
ADV/LD
			X Hold After CLK Rise	0.5	0.5
WE,		BW
	Hold After CLK Rise			0.5	0.5
CEN
Data Input Hold After CLK Rise				0.5	0.5
Chip Enable Hold After CLK Rise				0.5	0.5

ns

ns

ns

ns

ns

ns

Notes

15.This part has a voltage regulator internally; tPOWER is the time that the power is supplied above VDD(minimum) initially, before a read or write operation can be initiated.

16.tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of “AC Test Loads and Waveforms” on page 21. Transition is measured ±200 mV from steady-state voltage.

17.At any supplied voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z before Low-Z under the same system conditions.

18.This parameter is sampled and not 100% tested.

Document #: 001-15013 Rev. *E Page 22 of 30

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