Cypress CY7C1475BV25 Maximum Ratings, Electrical Characteristics, Operating Range, Range Ambient

CY7C1471BV25 CY7C1473BV25, CY7C1475BV25

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.

Storage Temperature		–65°C to +150°C
Ambient Temperature with
Power Applied		–55°C to +125°C
Supply Voltage on VDD Relative to GND		–0.5V to +3.6V
Supply Voltage on VDDQ Relative to GND		–0.5V to +VDD
DC Voltage Applied to Outputs
in Tri-State	–0.5V to VDDQ + 0.5V

Electrical Characteristics

Over the Operating Range [12, 13]

DC Input Voltage	–0.5V to VDD + 0.5V
Current into Outputs (LOW)	20 mA
Static Discharge Voltage	>2001V
(MIL-STD-883, Method 3015)
Latch Up Current	>200 mA

Operating Range

Range	Ambient	VDD	VDDQ
	Temperature
Commercial	0°C to +70°C	2.5V –5%/+5%	2.5V–5% to
			VDD
Industrial	–40°C to +85°C

Parameter	Description	Test Conditions		Min	Max	Unit
VDD	Power Supply Voltage			2.375	2.625	V
VDDQ	IO Supply Voltage	For 2.5V IO		2.375	VDD	V
VOH	Output HIGH Voltage	For 2.5V IO, IOH = –1.0 mA		2.0		V
VOL	Output LOW Voltage	For 2.5V IO, IOL= 1.0 mA			0.4	V
VIH	Input HIGH Voltage[12]	For 2.5V IO		1.7	VDD + 0.3V	V
VIL	Input LOW Voltage[12]	For 2.5V IO		–0.3	0.7	V
IX	Input Leakage Current	GND ≤ VI ≤ VDDQ		–5	5	μA
	except ZZ and MODE
	Input Current of MODE	Input = VSS		–30		μA
		Input = VDD			5	μA
	Input Current of ZZ	Input = VSS		–5		μA
		Input = VDD			30	μA
IOZ	Output Leakage Current	GND ≤ VI ≤ VDDQ, Output Disabled		–5	5	μA
IDD [14]	VDD Operating Supply	VDD = Max, IOUT = 0 mA,	6.5 ns cycle, 133 MHz		305	mA
	Current	f = fMAX = 1/tCYC
			8.5 ns cycle, 100 MHz		275	mA
ISB1	Automatic CE	VDD = Max, Device Deselected,	6.5 ns cycle, 133 MHz		170	mA
	Power Down	VIN ≥ VIH or VIN ≤ VIL
			8.5 ns cycle, 100 MHz		170	mA
	Current—TTL Inputs	f = fMAX, inputs switching
ISB2	Automatic CE	VDD = Max, Device Deselected,	All speeds		120	mA
	Power Down	VIN ≤ 0.3V or VIN > VDD – 0.3V,
	Current—CMOS Inputs	f = 0, inputs static
ISB3	Automatic CE	VDD = Max, Device Deselected, or	6.5 ns cycle, 133 MHz		170	mA
	Power Down	VIN ≤ 0.3V or VIN > VDDQ – 0.3V
			8.5 ns cycle, 100 MHz		170	mA
	Current—CMOS Inputs	f = fMAX, inputs switching
ISB4	Automatic CE	VDD = Max, Device Deselected,	All Speeds		135	mA
	Power Down	VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
	Current—TTL Inputs	f = 0, inputs static

Notes

12.Overshoot: VIH(AC) < VDD +1.5V (pulse width less than tCYC/2). Undershoot: VIL(AC) > –2V (pulse width less than tCYC/2).

13.TPower-up: assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

14.The operation current is calculated with 50% read cycle and 50% write cycle.

Document #: 001-15013 Rev. *E Page 20 of 30

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