Cypress CY7C1471BV25, CY7C1473BV25, CY7C1475BV25 Switching Waveforms

CY7C1471BV25

CY7C1473BV25, CY7C1475BV25

Document #: 001-15013 Rev. *E Page 23 of 30

Switching Waveforms

Figure 8 shows read-write timing waveform.[19, 20, 21]

Figure 8. Read/Write Timing

WRITE

D(A1)

123456789

CLK

tCYC

tCL

tCH

10 CE

tCEH

tCES

WE

CEN

tCENH

tCENS

BWX

ADV/LD

tAH

tAS

ADDRESS A1 A2 A3 A4 A5 A6 A7

tDH

tDS

DQ

C

OMMAND

tCLZ

D(A1) D(A2) Q(A4)Q(A3)

D(A2+1)

tDOH tCHZ

tCDV

WRITE

D(A2)

BURST

WRITE

D(A2+1)

READ

Q(A3)

READ

Q(A4)

BURST

READ

Q(A4+1)

WRITE

D(A5)

READ

Q(A6)

WRITE

D(A7)

DESELECT

OE

tOEV

tOELZ

tOEHZ

DON’T CARE UNDEFINED

D(A5)

tDOH

Q(A4+1)

D(A7)Q(A6)

Notes

19.For this waveform ZZ is tied LOW.

20.When CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW or CE3 is HIGH.

21.Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.

[+] Feedback

Contents

Main 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Features Functional Description Selection Guide CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Logic Block Diagram CY7C1471BV25 (2M x 36) C Logic Block Diagram CY7C1473BV25 (4M x 18) A DQPB CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev. *E Page 3 of 30 Logic Block Diagram CY7C1475BV25 (1M x 72) DQs DQPa DQPb DQPc DQPd DQPe DQPf DQPg DQPh CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Pin Configurations CY7C1471BV25 Figure 1. 100- Pin TQFP Pinout CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 CY7C1473BV25 Document #: 001-15013 Rev. *E Page 5 of 30 Figure 2. 100-Pin TQFP Pinout 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1471BV25 (2M x 36) 2345671 A B C D E F G H J K L M N P R 891011 CY7C1473BV25 (4M x 18) 2345671 A B C D E F G H J K L M N P R CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 CY7C1475BV25 (1M 72) A B C D E F G H J K L M N P R T U V W 123456789 1110 209-Ball FBGA (14 x 22 x 1.76 mm) Pinout Page Functional Overview Single Read Accesses Burst Read Accesses Single Write Accesses Burst Write Accesses ZZ Mode Electrical Characteristics Page Page IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature Test Access Port (TAP) Performing a TAP Reset CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 TAP Registers TAP Instruction Set Page 2.5V TAP AC Test Conditions TAP AC Switching Characteristics 50 TDO 1.25V 20pF Page Page Page Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance Switching Characteristics Switching Waveforms Figure 8 shows read-write timing waveform.[19, 20, 21] Figure 8. Read/Write Timing OE OMMAND BW Page CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Figure 10 shows ZZ Mode timing waveform.[23, 24] Figure 10. ZZ Mode Timing Switching Waveforms Ordering Information Package Diagrams Figure 11. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050 A Figure 12. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165 Package Diagrams 51-85165-*A Page Document History Page