Cypress CY7C1471BV25, CY7C1473BV25, CY7C1475BV25 CY7C1471BV25 CY7C1473BV25, CY7C1475BV25

CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Document #: 001-15013 Rev. *E Page 2 of 30
Logic Block Diagram – CY7C1471BV25 (2M x 36)
Logic Block Diagram – CY7C1473BV25 (4M x 18)
C
MODE
BW A
BW B
WE
CE1
CE2
CE3
OE READ LOGIC
DQs
DQP
A
DQP B
DQP C
DQP D
MEMORY
ARRAY
E
INPUT
REGISTER
BW C
BW D
ADDRESS
REGISTER
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
ADV/LD
CE ADV/LD
C
CLK
CEN
WRITE
DRIVERS
D
A
T
A
S
T
E
E
R
I
N
G
S
E
N
S
E
A
M
P
S
WRITE ADDRESS
REGISTER
A0, A1, A
O
U
T
P
U
T
B
U
F
F
E
R
S
E
ZZ SLEEP
CONTROL
C
MODE
BWA
BWB
WE
CE1
CE2
CE3
OE READ LOGIC
DQs
DQP
A
DQPB
MEMORY
ARRAY
E
INPUT
REGISTER
ADDRESS
REGISTER
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
ADV/LD
CE ADV/LD
C
CLK
C EN
WRITE
DRIVERS
D
A
T
A
S
T
E
E
R
I
N
G
S
E
N
S
E
A
M
P
S
WRITE ADDRESS
REGISTER
A0, A1, A
O
U
T
P
U
T
B
U
F
F
E
R
S
E
ZZ SLEEP
CONTROL
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