Cypress CY7C1475BV25 Logic Block Diagram CY7C1471BV25 2M x, Logic Block Diagram CY7C1473BV25 4M x

CY7C1471BV25 CY7C1473BV25, CY7C1475BV25

Logic Block Diagram – CY7C1471BV25 (2M x 36)

	A0, A1, A	ADDRESS	A1			A1'
		REGISTER
				D1	Q1
	MODE		A0	D0	Q0	A0'
		CE	ADV/LD		BURST
CLK	C				LOGIC
CEN			C
			WRITE ADDRESS
			REGISTER

											D
										S
											A
										E	T
ADV/LD										N	A
								MEMORY		S
BW A							WRITE
						WRITE REGISTRY		ARRAY		E	S
					B	AND DATA COHERENCY	DRIVERS				T
		BW								A
						CONTROL LOGIC					E
	BW C									M	E
										P	R
BW D
										S	I
			WE								N
											G
									INPUT	E
									REGISTER
				OE		READ LOGIC
			CE1
			CE2
			CE3
			ZZ			SLEEP
						CONTROL

Logic Block Diagram – CY7C1473BV25 (4M x 18)

A0, A1, A	ADDRESS	A1			A1'
	REGISTER		D1	Q1
MODE		A0	D0	Q0	A0'
				BURST

CLK	C	CE	ADV/LD	LOGIC
CEN			C
			WRITE ADDRESS
			REGISTER
						S	D
							A
						E	T
	ADV/LD					N	A
	BW A			WRITE	MEMORY	S
			WRITE REGISTRY		ARRAY	E	S
	BW B		AND DATA COHERENCY	DRIVERS		A	T
			CONTROL LOGIC				E
						M	E
						P	R
	WE					S	I
							N
							G
					INPUT	E
					REGISTER
	OE
			READ LOGIC
	CE1
	CE2
	CE3
	ZZ		SLEEP
			CONTROL

O

U

T

P

U

T

B

U

F

F

E

R

S

E

O

U

T

P

U

T

B

U

F

F

E

R

S

E

DQs

DQP A DQP B DQP C DQP D

DQs

DQPA DQPB

Document #: 001-15013 Rev. *E Page 2 of 30

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