CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Document #: 001-15013 Rev. *E Page 10 of 30
included to greatly simplify read/modify/write sequences, which
can be reduced to simple byte write operations.
Because the CY7C1471BV25, CY7C1473BV25, and
CY7C1475BV25 are common IO devices, data must not be
driven into the device while the outputs are active. The OE can
be deasserted HIGH before presenting data to the DQs and
DQPX inputs. This tri-states the output drivers. As a safety
precaution, DQs and DQPX are automatically tri-stated during
the data portion of a write cycle, regardless of the state of OE.

Burst Write Accesses

The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25
have an on-chip burst counter that makes it possible to supply a
single address and conduct up to four Write operations without
reasserting the address inputs. Drive ADV/LD LOW to load the
initial address, as described in the Single Write Access section.
When ADV/LD is driven HIGH on the subsequent clock rise, the
Chip Enables (CE1, CE2, and CE3) and WE inputs are ignored
and the burst counter is incremented. You must drive the correct
BWX inputs in each cycle of the Burst Write to write the correct
data bytes.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. You must
select the device before entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
Table 2. Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Table 3. Linear Burst Address Table
(MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min Max Unit
IDDZZ Sleep mode standby current ZZ > VDD – 0.2V 120 mA
tZZS Device operation to ZZ ZZ > VDD – 0.2V 2tCYC ns
tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns
tZZI ZZ active to sleep current This parameter is sampled 2tCYC ns
tRZZI ZZ Inactive to exit sleep current This parameter is sampled 0 ns
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