Texas Instruments TMS320DM355 warranty ASP as SPI Timing Requirements, M53 M54 M62, M56

TMS320DM355

Digital Media System-on-Chip (DMSoC)

www.ti.com

SPRS463A –SEPTEMBER 2007 –REVISED SEPTEMBER 2007

Table 5-43. ASP as SPI Timing Requirements

CLKSTP = 11b, CLKXP = 1 (see Figure 5-45)

NO.			MASTER	UNIT
			MIN
				MAX
M58	tsu(DRV-CKXL)	Setup time, DR valid before CLKX low	11	ns
M59	th(CKXL-DRV)	Hold time, DR valid after CLKX low	0	ns

Table 5-44. ASP as SPI Switching Characteristics(1) (2)

CLKSTP = 11b, CLKXP = 1 (see Figure 5-45)

NO.		PARAMETER	MASTER		UNIT
			MIN	MAX
M62	tc(CKX)	Cycle time, CLKX	38.5 or		ns
			2P(3)(3)
M53	t	Delay time, CLKX high to FSX high(4)	D – 1	D + 3	ns
	d(CKXH-FXH)
M54	t	Delay time, FSX low to CLKX low(5)	T – 2	T + 2	ns
	d(FXL-CKXL)
M55	td(CKXL-DXV)	Delay time, CLKX low to DX valid	–2	6	ns
M56	tdis(CKXH-DXHZ)	Disable time, DX high impedance following last data bit from	– 3	+ 3	ns
		CLKX high
M57	td(FXL-DXV)	Delay time, FSX low to DX valid	C – 1	C + 10	ns

(1)P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5) .

(2)T = CLKX period = (1 + CLKGDV) × P

C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) × P when CLKGDV is even

D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) × P when CLKGDV is even

(3)Use which ever value is greater.

(4)FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master ASP

(5)FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

CLKX
	M53	M54	M62
FSX
	M56	M57	M55
DX	Bit￿0	Bit(n-1)	(n-2)	(n-3)	(n-4)
		M58	M59
DR	Bit￿0	Bit(n-1)	(n-2)	(n-3)	(n-4)

Figure 5-45. ASP as SPI: CLKSTP = 11b, CLKXP = 1

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