Texas Instruments TMS320DM355 warranty ASP Electrical Data/Timing, Otgclks

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TMS320DM355

Digital Media System-on-Chip (DMSoC)

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SPRS463A –SEPTEMBER 2007 –REVISED SEPTEMBER 2007

5.14.1ASP Electrical Data/Timing

5.14.1.1Audio Serial Port (ASP) Timing

Table 5-35. Timing Requirements for ASP(1) (see Figure 5-41)

NO.				DM355	UNIT
				MIN
					MAX
15	tc(CLK)	Cycle time, CLK	CLK ext	38.5 or 2P(2)(3)	ns
16	OTG(CLKS)	Pulse duration, CLKR/X high or CLKR/X low	CLKS ext	19.25 or P(2)(3)(4)	ns
5	tsu(FRH-CKRL)	Setup time, external FSR high before CLKR low	CLKR int	21	ns
			CLKR ext	6
6	th(CKRL-FRH)	Hold time, external FSR high after CLKR low	CLKR int	0	ns
			CLKR ext	6
7	tsu(DRV-CKRL)	Setup time, DR valid before CLKR low	CLKR int	21	ns
			CLKR ext	6
8	th(CKRL-DRV)	Hold time, DR valid after CLKR low	CLKR int	0	ns
			CLKR ext	6
10	tsu(FXH-CKXL)	Setup time, external FSX high before CLKX low	CLKX int	21	ns
			CLKX ext	6
11	th(CKXL-FXH)	Hold time, external FSX high after CLKX low	CLKX int	0	ns
			CLKX ext	10

(1)CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

(2)P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5) .

(3)Use which ever value is greater.

(4)The ASP does not have a duty cycle specification, just ensure that the minimum pulse duration specification is met.

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