Manuals / Texas Instruments / Computer Equipment / Computer Hardware

Texas Instruments TMS320DM355 Recommended Clock and Control Signal Transition Behavior, Plane

Models: TMS320DM355

1 155

Download 155 pages 17.5 Kb

Page 96

TMS320DM355

Digital Media System-on-Chip (DMSoC)

www.ti.com

SPRS463A –SEPTEMBER 2007 –REVISED SEPTEMBER 2007

5.2 Recommended Clock and Control Signal Transition Behavior

All clocks and control signals should transition between VIH and VIL (or between VIL and VIH) in a monotonic manner.

5.3 Power Supplies

The power supplies of DM355 are summarized in Table 5-1.

Table 5-1. Power Supplies

Customer	Tolerance Package	Chip Plane
Board	Plane	Name
Supply

Description

Comments

PRODUCT PREVIEW

1.3 V

±5%

1.3 V

3.3 V

±5%

3.3 V

3.3 V	±5%	3.3 V
1.8 V	±5%	1.8 V
1.8 V	±5%	1.8 V
1.8 V	±5%	1.8 V
0 V	n/a	0 V
0 V	n/a	0 V
0 V	n/a	0 V
0 V	n/a	0 V
0 V	n/a	0 V
0 V	n/a	0 V
0 V	n/a	0 V
0 V	n/a	0 V

CVDD

VDDA_PLL1

VDDA_PLL2

VDDD13_USB

VDDA13_USB

VDD

VDD

VDD

VDD

VDDA33_DDRDLL

VDDA33_USB

VDDA33_USB_PLL

VDD

VDD_VIN

VDD_VOUT

VDD_DDR

VDDA18

VDDA18_DAC

VSS_MX1

VSS_MX2

VSS

VSSA

VSA_PLL1

VSSA_PLL2

VSSA_DLL

VSS_USB

Core VDD
PLL1 VDDA
PLL2 VDDA
USB 1.3 V supply
USB 1.3 V supply
IO VDD for LVCMOS	VDDSHV
IO VDD for MXI/O1	VDDSHV
IO VDD for MXI/O2	VDDSHV1
IO VDD for ISB DRVVBUS	VDDSHV2
DDR DLL analog VDD
Analog 3.3 V power USB PHY
Common mode 3.3 V power for USB
PHY (PLL)
IO VDD for peripherals
IO VDD for VideoIN I/F
IO VDD for VideoOUT I/F
	Analog 1.8 V power
	Place decoupling caps (0.1μF/10μf) close
	to chip
	Connect to external crystal capacitor
	ground
	Connect to external crystal capacitor
	ground
Chip ground
USB ESD ground
ground	VSS
ground	Keep separate from digital ground VSS
PLL1 VSSA
PLL2 VSSA
DLL ground
USB ground	VSSA13_USB
	VSSA13_USB
	VSSA33_USB
	VSSA33_USB_PLL

0 V	n/a	0 V	VSS_USB_REF
0 V	n/a	0 V	VSSA_DAC
VDDS*0.5		VDDS*0.5	VREFSSTL
5 V		5 V	USB_VBUS

USB PHY reference ground	VSSREF
DAC ground	Keep separate from digital ground VSS
DRR ref voltage	VDDS divided by 2, through board resistors
VBUS	Connect to external charge pump

96

Peripheral Information and Electrical Specifications

Submit Documentation Feedback

Image 96

Texas Instruments TMS320DM355 Recommended Clock and Control Signal Transition Behavior, Power Supplies, Tolerance Package

Contents

Features TMS320DM355 Digital Media System-on-Chip DMSoCTMS320DM355 Digital Media System-on-Chip DMSoC Description Functional Block Diagram Functional Block DiagramContents ARM926EJ-S Risc CPUDevice Characteristics Characteristics of the ProcessorHardware Features DM355DM355 ARM Configuration Bus Access to Peripherals Memory Map SummaryDM355 Memory Map Edma USBAddress Pin Assignments Pin Map Bottom ViewPin Map Quadrant B Pin Map Quadrant C Pin Map Quadrant D CCD Controller Signals for Each Input Mode Pin FunctionsImage Data Input Video Processing Front End PIN Name CCDCCD Controller/Video Input Terminal Functions Terminal Name noType DescriptionImage Data Output Video Processing Back End Vpbe CamhdCamvd Camwen FIELD\ R5 GIO083 PCLK/ T3 GIO082Signals for Vpbe Display Modes PIN NameYCC8 Prgb Srgb REC656Digital Video Terminal Functions Terminal NameAsynchronous External Memory Interface Aemif Analog Video Terminal FunctionsAsynchronous EMIF/NAND/OneNAND Terminal Functions TerminalType 1 Other 2 ZvddEMBA1 EMBA0DDR Memory Interface 10. DDR Terminal FunctionsDDRDQ14 DDRDQ13DDRDQ12 DDRDQ11Gpio 11. Gpio Terminal FunctionsUART2R MMCSD1 UART2C MMCSD1ASP0FS ASP0CLAsync Emif Data Bus bit01 GIO039 J17 Type 1 Other 2 3 Description PWM3B COUT1RTO0 COUT6 PWM1 COUT7Camwe Nfield / R5 GIO083 Camvd SPI2SDI SPI2SDESPI0SDI Multi-Media Card/Secure Digital MMC/SD Interfaces 12. MMC/SD Terminal FunctionsUniversal Serial Bus USB Interface Audio Interfaces13. USB Terminal Functions 14. ASP Terminal FunctionsUart Interface 15. Uart Terminal Functions10 I2C Interface Serial Interface16. I2C Terminal Functions 17. SPI Terminal FunctionsClock Interface 18. Clocks Terminal FunctionsReal Time Output RTO Interface Pulse Width Modulator PWM Interface19. RTO Terminal Functions 20. PWM Terminal FunctionsSystem Configuration Interface 21. System/Boot Terminal FunctionsPWM3B Field PWM3DEmulation 22. Emulation Terminal FunctionsPin List 23. DM355 Pin DescriptionsBGA GIO M4 I/O CcdcPINMUX08.CIN32 PINMUX09.CIN10R3 I/O Ccdc Camhd Ccdc Camvd CcdcCamwenfie Ccdc PINMUX011.CAMPWM2A / RTO0 PWM2B / RTO1PWM2C / RTO2 PWM2D / RTO3Reset Description Mux Control Reset Description Name BGA Type GroupState PWR Ddri GND DdrdPWR Ddrd Ddrzn Ddri AemiGroup AECFG1 GIOAECFG0 GIO PINMUX21.EMA0 GIO EMIF2PINMUX24.EMD1 PINMUX25.EMD7 PINMUX26.EMCEPINMUX27.EMCE PINMUX28.EMW EOE GIOPINMUX29.EMW AIT GIOMMCSD1DAT MMCSD1 DATA3 PINMUX398.GIO2UART2RTS GIO Uart UART2 RTS MMCSD1DATPINMUX324.GIO1 GIO SPI1SDENA1PINMUX327.GIO8 PINMUX328.GIO7Usbvbus Usbp Usbdrvvbu UsbpGND Usbp PWR UsbpReset ASP1CLKXASP1FSX ASP1CLKRRSV03 RSV04 RSV05 RSV06 RSV07 CvddType Group Cvdd PWR K10 Device Support Development ToolsDevice Nomenclature Software Development ToolsDevice Documentation Related Documentation From Texas InstrumentsProduct Preview SPRUF71 ARM Subsystem Overview Components of the ARM SubsystemARM926EJ-S Risc CPU 1 CP15 2 MMUCaches and Write Buffer Tightly Coupled Memory TCM Advanced High-performance Bus AHBEmbedded Trace Macrocell ETM and Embedded Trace Buffer ETB Memory MappingExternal Memories PeripheralsARM Interrupt Controller Aintc Interrupt MappingAintc Interrupt Connections Interrupt Acronym SourceNumber Device Clocking OverviewPreview Supported Clocking Configurations for DM355-216 ARM Vpss VCOPlldiv Syscl Sysclk PLLDIV3 PLLDIV4 Supported Clocking Configurations for DM355-270 PredMpeg and Jpeg PLLDIV1 Sysc Plldi SYSCLK2 PLLDIV3 Sysclk PLLDIV4 SYSCLK4Prediv Pllm PostdiPlldiv Sysc SYSCLK2 PLLDIV3 Syscl PLLDIV4 SYSCLK4 Peripheral Clocking Considerations Video Processing Back End ClockingUSB Clocking Product Preview PLL Controller Pllc PLL Controller ModulePLLC1 10. PLLC1 Output ClocksPLLC1 Configuration In DM355 TMS320DM355PLLC2 Configuration in DM355 PLLC211. PLLC2 Output Clocks SYSCLK1 DDR PHYPower and Sleep Controller PSC System Control ModulePin Multiplexing Hardware Controlled Pin Multiplexing12. Peripheral Pin Mux Overview Peripheral Muxed With Primary Function Secondary FunctionDevice Reset 13. Aecfg Async Emif Configuration Pin Mux Coding14. Reset Types Software Controlled Pin MultiplexingDefault Device Configurations Device Configuration Pins15. Device Configuration Device Configuration AffectedPLL Configuration Power Domain and Module State Configuration16. Module Configuration Default StatesModule ARM Boot Mode Configuration Aemif ConfigurationDevice Boot Modes Boot Modes Overview Power Management Boot Mode Functional Block Diagram17. Power Management Features Power Management Features Description14 64-Bit Crossbar Architecture Crossbar ConnectionsEdma Controller 18. Crossbar Connection MatrixProduct Preview Edma Channel Synchronization Events 19. Edma Channel Synchronization Events1Edma Event Name Event Description Channel MPEG/JPEG Overview 19. Edma Channel Synchronization EventsDevice Operating Conditions VbusRecommended Operating Conditions MIN NOM MAX UnitCV DD USB UsbvbusParameter Test ConditionsMIN TYP MAX Unit Signal Transition Levels Parameter Information Device-Specific InformationTester PinElectronics Output Under TestTiming Parameters and Board Routing Analysis Recommended Clock and Control Signal Transition Behavior Power SuppliesPower Supplies Tolerance PackagePower-Supply Sequencing Power-Supply Design ConsiderationsPower-Supply Decoupling Reset Reset Electrical Data/TimingTiming Requirements for Reset 1 2 see Figure MINOscillators and Clocks 1 MXI1 24-MHz Oscillator2 MXI2 27-MHz Oscillator optional oscillator Parameter MIN TYP MAX UnitESR MXI2 MXO2Clock PLL Electrical Data/Timing Input and Output Clocks Timing Requirements for MXI1/CLKIN11 2 see FigureMIN TYP MAX MXI/CLKINUNI MXI/CLKIN CLKOUT111. CLKOUT3 Timing General-Purpose Input/Output Gpio Gpio Peripheral Input/Output Electrical Data/Timing10. Timing Requirements for Gpio Inputs see Figure MIN Unit MAXGpio Peripheral External Interrupts Electrical Data/Timing GPIx GPOxEXTINTx External Memory Interface Emif Asynchronous Emif AemifNand NAND, SmartMedia, xD OneNANDReads WritesMAX T DM355 MINNom RST*EUNI MAX T WS+WST+WH*E WS+WST+WH+EWOutput hold time, Emwe high to WH*E EMD150 invalid EMCE10 EMA130Emoe EMD150EMA130 EMD150 Emoe EmwaitEmwe Emwait 18. Synchronous OneNAND Flash Read Timing 2 DDR2 Memory Controller 2.1 DDR2/mDDR Memory Controller Electrical Data/TimingFast Mode Standard Mode Unit MIN MAX Parameter Fast Mode Standard Unit MIN MAXMMC/SD 1 MMC/SD Electrical Data/TimingSdclk Sdcmd Start Xmit ENDSdclk Start ENDVideo Processing Sub-System Vpss Overview Video Processing Front-End VpfeCCD Controller Ccdc Ipipe Image Pipe SdramHardware 3A H3A DM355-216 DM355-270 MIN MAXPclk HD/VD 11,13 12,14CWE/CFIELD CI70/YI70 CCD130Video Processing Back-End Vpbe On-Screen Display OSDVideo Encoder / Digital LCD Controller VENC/DLCD CGMS/WSSPclk Extclk MINVclkina VctlbVctl B Vdatac Vclkin a VclkVrefibias Iout VFBMSB 32. DAC With Buffer Circuit Tvoutv10 USB 10.1 USB2.0 Electrical Data/TimingParameter LOW Speed Full Speed High Speed Unit MbpsUsbdm 10%V OL 90%V OHUsbdp Universal Asynchronous Receiver/Transmitter Uart Uart Electrical Data/Timing26. Timing Requirements for UARTx Receive see Figure 35. Uart Transmit/Receive Timing UARTTXDn UARTRXDn Start Bit DataBitsSerial Port Interface SPI SPI Electrical Data/Timing28. Timing Requirements for SPI All Modes1 see Figure SPIxCLK ClockPolarity=037. SPI Master Mode External Timing Clock Phase = SpienSpien Spiclk Spidi Msbin Data LsbinInput Spido Msbout Data LsboutInter-Integrated Circuit I2C Standard Fast Mode Unit MIN MAX 13.1 I2C Electrical Data/TimingSDA SCL Stop Start Repeated34. Switching Characteristics for I2C Timings1 see Figure Parameter Standard Fast Mode Unit MIN MAXStop Start StopAudio Serial Port ASP ASP Electrical Data/Timing OtgclksClks Clkr ClkxFSX 38. ASP as SPI Switching Characteristics1 37. ASP as SPI Timing RequirementsMaster Unit MIN MAX Parameter Master Unit MIN MAX40. ASP as SPI Switching Characteristics1 39. ASP as SPI Timing RequirementsM34 M35 M42 M37 M38 M36 Bit0 Bitn-1 M39 M4042. ASP as SPI Switching Characteristics1 41. ASP as SPI Timing RequirementsM43 M44 M52 M46 M45 Bit0 Bitn-1 M49 M5044. ASP as SPI Switching Characteristics1 43. ASP as SPI Timing RequirementsM53 M54 M62 M56Timer Timer Electrical Data/Timing45. Timing Requirements for Timer Input1 2 3 see Figure TiminPulse Width Modulator PWM 16.1 PWM0/1/2/3 Electrical/Timing DataPWM0/1/2/3 48. PWM Output Delay Timing Vdccdc PWM0 Invalid PWM1 PWM2 PWM3 ValidReal Time Out RTO RTO Electrical/Timing DataRTO0/1/2/3 RTO0Ieee 1149.1 Jtag Jtag Test-Port Electrical Data/Timing 48. Timing Requirements for Jtag Test Port see FigureTCK Rtck TDO TDI TMS 52. Jtag Output Timing Rtck TDORevision History ADDS/CHANGES/DELETESRevision History Thermal Resistance Characteristics Pbga Package ZCE Thermal Data for ZCEPackaging Information ΜC/WPage Products Applications DSPRfid