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Texas Instruments TMS320DM355 13.1 I2C Electrical Data/Timing, Standard Fast Mode Unit MIN MAX

Models: TMS320DM355

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TMS320DM355

Digital Media System-on-Chip (DMSoC)

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SPRS463A –SEPTEMBER 2007 –REVISED SEPTEMBER 2007

5.13.1I2C Electrical Data/Timing

5.13.1.1Inter-Integrated Circuits (I2C) Timing

Table 5-33. Timing Requirements for I2C Timings(1) (see Figure 5-39)

NO.

1 tc(SCL)

2tsu(SCLH-SDAL)

3th(SCLL-SDAL)

4 tw(SCLL)

5 tw(SCLH)

6tsu(SDAV-SCLH)

7th(SDA-SCLL)

8tw(SDAH)

9 tr(SDA)

10tr(SCL)

11 tf(SDA)

12 tf(SCL)

13tsu(SCLH-SDAH)

14 tw(SP)

15 Cb (5)

Cycle time, SCL

Setup time, SCL high before SDA low (for a repeated START condition)

Hold time, SCL low after SDA low (for a START and a repeated START condition)

Pulse duration, SCL low

Pulse duration, SCL high

Setup time, SDA valid before SCL high

Hold time, SDA valid after SCL low (For I2C bus™ devices)

Pulse duration, SDA high between STOP and START conditions

Rise time, SDA

Rise time, SCL

Fall time, SDA

Fall time, SCL

Setup time, SCL high before SDA high (for STOP condition)

Pulse duration, spike (must be suppressed)

Capacitive load for each bus line

DM355

STANDARD

FAST MODE

UNIT

MODE

 

 

 

 

MIN MAX

MIN

MAX

 

10

 

2.5

 

μs

4.7

 

0.6

 

μs

4

 

0.6

 

μs

4.7

 

1.3

 

μs

4

 

0.6

 

μs

250

100(2)

 

ns

0(3)

0(3)

0.9(4)

μs

4.7

 

1.3

 

μs

1000

20 + 0.1C

(5)

300

ns

 

 

b

 

 

1000

20 + 0.1C

(5)

300

ns

 

 

b

 

 

300

20 + 0.1C

(5)

300

ns

 

 

b

 

 

300

20 + 0.1C

(5)

300

ns

 

 

b

 

 

4

 

0.6

 

μs

 

 

0

50

ns

400

 

 

400

pF

PRODUCT PREVIEW

(1)The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.

(2) A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus™ system, but the requirement tsu(SDA-SCLH)≥250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch

the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns (according to the Standard-mode I2C-Bus Specification) before the SCL line is released.

(3)A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.

(4)The maximum th(SDA-SCLL)has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.

(5)Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

11

SDA

8

4 10

SCL

1

7

3

Stop Start

6

5

12

Repeated

Start

3

2

9

14

13

Stop

Figure 5-39. I2C Receive Timings

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Peripheral Information and Electrical Specifications

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Texas Instruments TMS320DM355 warranty 13.1 I2C Electrical Data/Timing, Standard Fast Mode Unit MIN MAX, Sda Scl
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TMS320DM355 specifications

The Texas Instruments TMS320DM355 is a versatile digital signal processor designed to support a wide array of multimedia applications, specifically in the realms of digital video and audio processing. As part of the TMS320 family of digital signal processors, the DM355 brings a blend of computational power, energy efficiency, and integrated features that make it highly effective for tasks such as video encoding, decoding, and general signal processing.

One of the standout features of the DM355 is its advanced DaVinci architecture, which is specifically optimized for multimedia tasks. This architecture integrates both DSP and application processing functionalities. The dual-core architecture includes a high-performance DSP core that specializes in real-time signal processing alongside an ARM926EJ-S RISC microprocessor, facilitating the execution of complex algorithms and control tasks.

The DM355 offers robust multimedia processing capabilities with support for several video formats, including MPEG-2, MPEG-4, H.264, and JPEG. This enables developers to create powerful video applications for a variety of devices, from industrial systems to consumer electronics. Its processing capabilities extend to audio processing, allowing it to efficiently handle audio codecs and enhance audio quality in applications ranging from IP cameras to set-top boxes.

In terms of connectivity, the TMS320DM355 supports various interfaces including USB 2.0, Ethernet, and various serial interfaces like UART, SPI, and I2C. This wide range of connectivity options ensures that the DM355 can easily interface with different peripherals and network components, making it a suitable choice for networked applications.

Energy efficiency is another significant advantage of the DM355. With a focus on low power consumption, the device is designed to operate effectively in battery-powered and heat-sensitive environments. Its low thermal design power allows for extended operational life and reduced thermal management requirements, making it ideal for portable devices.

Furthermore, the DM355 is supported by a comprehensive software development framework, including the TI Code Composer Studio and a range of middleware tools, which streamline application development and speed up time to market. Its rich ecosystem enhances its usability across different applications, ensuring that developers can leverage the full potential of the hardware.

In summary, the Texas Instruments TMS320DM355 stands out as a powerful yet cost-effective DSP solution, combining advanced multimedia processing capabilities, robust connectivity options, and energy efficiency. Its unique architecture and extensive support resources make it a preferred choice for developers seeking to create innovative multimedia solutions.