Texas Instruments TMS320DM355 warranty Pclk Extclk, Min

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TMS320DM355

Digital Media System-on-Chip (DMSoC)

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SPRS463A –SEPTEMBER 2007 –REVISED SEPTEMBER 2007

∙Internal Color Bar Generation (100%/75%)

∙YUV/RGB modes support HDTV output (720p/1080i) with 74.25 MHz external clock input

5.9.2.3VPBE Electrical Data/Timing

Table 5-21. Timing Requirements for VPBE CLK Inputs (see Figure 5-27)

NO.			DM355		UNIT
			MIN	MAX
1	t	Cycle time, PCLK(1)	13.33	160	ns
	c(PCLK)
2	tw(PCLKH)	Pulse duration, PCLK high	5.7		ns
3	tw(PCLKL)	Pulse duration, PCLK low	5.7		ns
4	tt(PCLK)	Transition time, PCLK		3	ns
5	tc(EXTCLK)	Cycle time, EXTCLK	13.33	160	ns
6	tw(EXTCLKH)	Pulse duration, EXTCLK high	5.7		ns
7	tw(EXTCLKL)	Pulse duration, EXTCLK low	5.7		ns
8	tt(EXTCLK)	Transition time, EXTCLK		3	ns

(1)When the CCDC is used, the PCLK frequency must be less than or equal to half the VPSS clock frequency—i.e., PCLK ≤ SYSCLK4/2.

		3
2	1
PCLK
6	4	7	4
	5
EXTCLK
	8		8

Figure 5-27. VPBE PCLK and EXTCLK Timing

Table 5-22. Timing Requirements for VPBE Control Input With Respect to PCLK and EXTCLK(1) (2) (3) (see

Figure 5-28)

NO.			DM355	UNIT
			MIN
				MAX
9	tsu(VCTLV-VCLKIN)	Setup time, VCTL valid before VCLKIN edge	2	ns
10	th(VCLKIN-VCTLV)	Hold time, VCTL valid after VCLKIN edge	1	ns

(1)The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising edge of VCLKIN is referenced. When in negative edge clocking mode, the falling edge of VCLKIN is referenced.

(2)VCTL = HSYNC, VSYNC, and FIELD

(3)VCLKIN = PCLK or EXTCLK

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