Texas Instruments TMS320DM355 Asynchronous External Memory Interface Aemif, Terminal, Other

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TMS320DM355

Digital Media System-on-Chip (DMSoC)

www.ti.com

SPRS463A –SEPTEMBER 2007 –REVISED SEPTEMBER 2007

Table 2-8. Analog Video Terminal Functions

TERMINAL		TYPE (1)	OTHER (2)	DESCRIPTION
NAME	NO.
VREF	J7	A I/O/Z		Video DAC: Reference voltage output (0.45V, 0.1uF to GND). When the DAC is not
				used, the VREF signal should be connected to VSS.
IOUT	E1	A I/O/Z		Video DAC: Pre video buffer DAC output (1000 ohm to VFB). When the DAC is not
				used, the IOUT signal should be connected to VSS.
				Video DAC: External resistor (2550 Ohms to GND) connection for current bias
IBIAS	F2	A I/O/Z		configuration. When the DAC is not used, the IBIAS signal should be connected to
				VSS.
VFB	G1	A I/O/Z		Video DAC: Pre video buffer DAC output (1000 Ohms to IOUT, 1070 Ohms to
				TVOUT). When the DAC is not used, the VFB signal should be connected to VSS.
				Video DAC: Analog Composite NTSC/PAL output (SeeFigure 5-31andFigure 5-32for
TVOUT	F1	A I/O/Z	V	circuit connection). When the DAC is not used, the TVOUT signal should be left as a
				No Connect or connected to VSS.
VDDA18_DAC	L7	PWR		Video DAC: Analog 1.8V power. When the DAC is not used, the VDDA18_DAC signal
				should be connected to VSS.
VSSA_DAC	L8	GND		Video DAC: Analog 1.8V ground. When the DAC is not used, the VSSA_DAC signal
				should be connected to VSS.

(1)I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal. Specifies the operating I/O supply voltage for each signal. See Section 5.3, Power Supplies for more detail.

(2)PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)

2.4.3Asynchronous External Memory Interface (AEMIF)

The Asynchronous External Memory Interface (AEMIF) signals support AEMIF, NAND, and OneNAND.

Table 2-9. Asynchronous EMIF/NAND/OneNAND Terminal Functions

TERMINAL		TYPE (1)	OTHER (2) (3)
NAME	NO.
EM_A13/			PD
GIO067/	V19	I/O/Z
			VDD
BTSEL[1]
EM_A12/			PD
GIO066/	U19	I/O/Z
			VDD
BTSEL[0]
EM_A11/			PU
GIO065/	R16	I/O/Z
			VDD
AECFG[3]
EM_A10/			PU
GIO064/	R18	I/O/Z
			VDD
AECFG[2]
EM_A09/			PD
GIO063/	P17	I/O/Z
			VDD
AECFG[1]
EM_A08/			PD
GIO062/	T19	I/O/Z
			VDD
AECFG[0]
EM_A07/	P16	I/O/Z	VDD
GIO061

DESCRIPTION

Async EMIF: Address bus bit[13]

GIO: GIO[67]

System: BTSEL[1:0] sampled at power-on-reset to determine boot method. Used to drive boot status LED signal (active low) in ROM boot modes.

Async EMIF: Address bus bit[12]

GIO: GIO[66]

System: BTSEL[1:0] sampled at power-on-reset to determine boot method.

Async EMIF: Address bus bit[11]

GIO: GIO[65]

AECFG[3:0] sampled at power-on-reset to AECFG configuration. AECFG[3] sets default for PinMux2_EM_D15_8: AEMIF default bus width (16 or 8 bits)

Async EMIF: Address bus bit[10]

GIO: GIO[64]

AECFG[3:0] sampled at power-on-reset to AECFG configuration. AECFG[2:1] sets default for PinMux2_EM_BA0: AEMIF EM_BA0 definition (EM_BA0, EM_A14, GIO[054], rsvd)

Async EMIF: Address bus bit[09]

GIO: GIO[63]

AECFG[3:0] sampled at power-on-reset to AECFG configuration. AECFG[2:1] sets default for PinMux2_EM_BA0: AEMIF EM_BA0 definition (EM_BA0, EM_A14, GIO[054], rsvd)

Async EMIF: Address bus bit[08]

GIO: GIO[62]

AECFG[0] sets default for:

∙PinMux2_EM_A0_BA1: AEMIF address width (OneNAND or NAND)

∙PinMux2_EM_A13_3: AEMIF address width (OneNAND or NAND)

Async EMIF: Address bus bit[07]

GIO: GIO[61]

(1)I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2)Specifies the operating I/O supply voltage for each signal. See Section 5.3, Power Supplies for more detail.

(3)PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)

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