Jtag Output Timing, Rtck TDO | Texas Instruments TMS320DM355

PRODUCT PREVIEW

TMS320DM355

Digital Media System-on-Chip (DMSoC)

www.ti.com

SPRS463A –SEPTEMBER 2007 –REVISED SEPTEMBER 2007

Table 5-49. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port

(see Figure 5-51)

NO.

PARAMETER

DM355

UNIT

MIN

MAX

tc(RTCK)

Cycle time, RTCK

tw(RTCKH)

Pulse duration, RTCK high

tw(RTCKL)

Pulse duration, RTCK low

tr(all JTAG outputs)

Rise time, all JTAG outputs

1.3

tf(all JTAG outputs)

Fall time, all JTAG outputs

1.3

td(RTCKL-TDOV)

Delay time, TCK low to TDO valid

0.25*tc(RT

CK)

RTCK

TDO

Figure 5-52. JTAG Output Timing

150

Peripheral Information and Electrical Specifications

Submit Documentation Feedback

Page 150

Image 150

Texas Instruments TMS320DM355 warranty Jtag Output Timing, Rtck TDO

TMS320DM355 specifications

The Texas Instruments TMS320DM355 is a versatile digital signal processor designed to support a wide array of multimedia applications, specifically in the realms of digital video and audio processing. As part of the TMS320 family of digital signal processors, the DM355 brings a blend of computational power, energy efficiency, and integrated features that make it highly effective for tasks such as video encoding, decoding, and general signal processing.

One of the standout features of the DM355 is its advanced DaVinci architecture, which is specifically optimized for multimedia tasks. This architecture integrates both DSP and application processing functionalities. The dual-core architecture includes a high-performance DSP core that specializes in real-time signal processing alongside an ARM926EJ-S RISC microprocessor, facilitating the execution of complex algorithms and control tasks.

The DM355 offers robust multimedia processing capabilities with support for several video formats, including MPEG-2, MPEG-4, H.264, and JPEG. This enables developers to create powerful video applications for a variety of devices, from industrial systems to consumer electronics. Its processing capabilities extend to audio processing, allowing it to efficiently handle audio codecs and enhance audio quality in applications ranging from IP cameras to set-top boxes.

In terms of connectivity, the TMS320DM355 supports various interfaces including USB 2.0, Ethernet, and various serial interfaces like UART, SPI, and I2C. This wide range of connectivity options ensures that the DM355 can easily interface with different peripherals and network components, making it a suitable choice for networked applications.

Energy efficiency is another significant advantage of the DM355. With a focus on low power consumption, the device is designed to operate effectively in battery-powered and heat-sensitive environments. Its low thermal design power allows for extended operational life and reduced thermal management requirements, making it ideal for portable devices.

Furthermore, the DM355 is supported by a comprehensive software development framework, including the TI Code Composer Studio and a range of middleware tools, which streamline application development and speed up time to market. Its rich ecosystem enhances its usability across different applications, ensuring that developers can leverage the full potential of the hardware.

In summary, the Texas Instruments TMS320DM355 stands out as a powerful yet cost-effective DSP solution, combining advanced multimedia processing capabilities, robust connectivity options, and energy efficiency. Its unique architecture and extensive support resources make it a preferred choice for developers seeking to create innovative multimedia solutions.

Contents

Features TMS320DM355 Digital Media System-on-Chip DMSoC TMS320DM355 Digital Media System-on-Chip DMSoC Description Functional Block Diagram Functional Block Diagram Contents ARM926EJ-S Risc CPU Hardware Features Device CharacteristicsCharacteristics of the Processor DM355 DM355 Memory Map DM355 ARM Configuration Bus Access to PeripheralsMemory Map Summary Edma USB Address Pin Assignments Pin Map Bottom View Pin Map Quadrant B Pin Map Quadrant C Pin Map Quadrant D Image Data Input Video Processing Front End CCD Controller Signals for Each Input ModePin Functions PIN Name CCD Type CCD Controller/Video Input Terminal FunctionsTerminal Name no Description Camvd Image Data Output Video Processing Back End VpbeCamhd Camwen FIELD\ R5 GIO083 PCLK/ T3 GIO082 YCC8 Prgb Srgb Signals for Vpbe Display ModesPIN Name REC656 Digital Video Terminal Functions Terminal Name Asynchronous EMIF/NAND/OneNAND Terminal Functions Asynchronous External Memory Interface AemifAnalog Video Terminal Functions Terminal EMBA1 Type 1 Other 2Zvdd EMBA0 DDR Memory Interface 10. DDR Terminal Functions DDRDQ12 DDRDQ14DDRDQ13 DDRDQ11 Gpio 11. Gpio Terminal Functions ASP0FS UART2R MMCSD1UART2C MMCSD1 ASP0CL Async Emif Data Bus bit01 GIO039 J17 Type 1 Other 2 3 Description PWM3B COUT1 RTO0 COUT6 PWM1 COUT7Camwe Nfield / R5 GIO083 Camvd SPI2SDI SPI2SDESPI0SDI Multi-Media Card/Secure Digital MMC/SD Interfaces 12. MMC/SD Terminal Functions 13. USB Terminal Functions Universal Serial Bus USB InterfaceAudio Interfaces 14. ASP Terminal Functions Uart Interface 15. Uart Terminal Functions 16. I2C Terminal Functions 10 I2C InterfaceSerial Interface 17. SPI Terminal Functions Clock Interface 18. Clocks Terminal Functions 19. RTO Terminal Functions Real Time Output RTO InterfacePulse Width Modulator PWM Interface 20. PWM Terminal Functions PWM3B Field System Configuration Interface21. System/Boot Terminal Functions PWM3D Emulation 22. Emulation Terminal Functions Pin List 23. DM355 Pin DescriptionsBGA PINMUX08.CIN32 GIOM4 I/O Ccdc PINMUX09.CIN10 R3 I/O Ccdc Camwenfie Ccdc Camhd CcdcCamvd Ccdc PINMUX011.CAM PWM2C / RTO2 PWM2A / RTO0PWM2B / RTO1 PWM2D / RTO3 Reset Description Mux Control Reset Description Name BGA Type GroupState PWR Ddrd Ddrzn Ddri PWR DdriGND Ddrd Aemi Group AECFG1 GIOAECFG0 GIO PINMUX21.EMA0 GIO EMIF2PINMUX24.EMD1 PINMUX25.EMD7 PINMUX26.EMCEPINMUX27.EMCE PINMUX29.EMW PINMUX28.EMWEOE GIO AIT GIO UART2RTS GIO Uart MMCSD1DATMMCSD1 DATA3 PINMUX398.GIO2 UART2 RTS MMCSD1DAT PINMUX327.GIO8 PINMUX324.GIO1GIO SPI1SDENA1 PINMUX328.GIO7 GND Usbp Usbvbus UsbpUsbdrvvbu Usbp PWR Usbp ASP1FSX ResetASP1CLKX ASP1CLKR RSV03 RSV04 RSV05 RSV06 RSV07 CvddType Group Cvdd PWR K10 Device Nomenclature Device SupportDevelopment Tools Software Development Tools Device Documentation Related Documentation From Texas Instruments Product Preview SPRUF71 ARM Subsystem Overview Components of the ARM Subsystem ARM926EJ-S Risc CPU 1 CP15 2 MMUCaches and Write Buffer Embedded Trace Macrocell ETM and Embedded Trace Buffer ETB Tightly Coupled Memory TCMAdvanced High-performance Bus AHB Memory Mapping ARM Interrupt Controller Aintc External MemoriesPeripherals Interrupt Mapping Aintc Interrupt Connections Interrupt Acronym SourceNumber Device Clocking Overview Preview Supported Clocking Configurations for DM355-216 ARM Vpss VCOPlldiv Syscl Sysclk PLLDIV3 PLLDIV4 Mpeg and Jpeg Supported Clocking Configurations for DM355-270Pred PLLDIV1 Sysc Plldi SYSCLK2 PLLDIV3 Sysclk PLLDIV4 SYSCLK4 Prediv Pllm PostdiPlldiv Sysc SYSCLK2 PLLDIV3 Syscl PLLDIV4 SYSCLK4 Peripheral Clocking Considerations Video Processing Back End ClockingUSB Clocking Product Preview PLL Controller Pllc PLL Controller Module PLLC1 10. PLLC1 Output Clocks PLLC1 Configuration In DM355 TMS320DM355 11. PLLC2 Output Clocks PLLC2 Configuration in DM355PLLC2 SYSCLK1 DDR PHY Power and Sleep Controller PSC System Control Module 12. Peripheral Pin Mux Overview Pin MultiplexingHardware Controlled Pin Multiplexing Peripheral Muxed With Primary Function Secondary Function 14. Reset Types Device Reset13. Aecfg Async Emif Configuration Pin Mux Coding Software Controlled Pin Multiplexing 15. Device Configuration Default Device ConfigurationsDevice Configuration Pins Device Configuration Affected PLL Configuration Power Domain and Module State Configuration 16. Module Configuration Default StatesModule ARM Boot Mode Configuration Aemif ConfigurationDevice Boot Modes Boot Modes Overview Power Management Boot Mode Functional Block Diagram 17. Power Management Features Power Management Features Description Edma Controller 14 64-Bit Crossbar ArchitectureCrossbar Connections 18. Crossbar Connection Matrix Product Preview Edma Channel Synchronization Events 19. Edma Channel Synchronization Events1Edma Event Name Event Description Channel MPEG/JPEG Overview 19. Edma Channel Synchronization Events Device Operating Conditions Vbus CV DD Recommended Operating ConditionsMIN NOM MAX Unit USB Usbvbus Parameter Test ConditionsMIN TYP MAX Unit Tester PinElectronics Signal Transition LevelsParameter Information Device-Specific Information Output Under Test Timing Parameters and Board Routing Analysis Power Supplies Recommended Clock and Control Signal Transition BehaviorPower Supplies Tolerance Package Power-Supply Sequencing Power-Supply Design ConsiderationsPower-Supply Decoupling Timing Requirements for Reset 1 2 see Figure ResetReset Electrical Data/Timing MIN Oscillators and Clocks 1 MXI1 24-MHz Oscillator ESR 2 MXI2 27-MHz Oscillator optional oscillatorParameter MIN TYP MAX Unit MXI2 MXO2 MIN TYP MAX Clock PLL Electrical Data/Timing Input and Output ClocksTiming Requirements for MXI1/CLKIN11 2 see Figure MXI/CLKIN UNI MXI/CLKIN CLKOUT1 11. CLKOUT3 Timing 10. Timing Requirements for Gpio Inputs see Figure General-Purpose Input/Output GpioGpio Peripheral Input/Output Electrical Data/Timing MIN Unit MAX Gpio Peripheral External Interrupts Electrical Data/Timing GPIx GPOxEXTINTx Nand NAND, SmartMedia, xD External Memory Interface EmifAsynchronous Emif Aemif OneNAND Reads WritesMAX T UNI MAX T DM355 MINNomRST*E WS+WST+WH*E WS+WST+WH+EW Emoe Output hold time, Emwe high to WH*E EMD150 invalid EMCE10EMA130 EMD150 EMA130 EMD150 Emoe EmwaitEmwe Emwait 18. Synchronous OneNAND Flash Read Timing 2 DDR2 Memory Controller 2.1 DDR2/mDDR Memory Controller Electrical Data/Timing MMC/SD Fast Mode Standard Mode Unit MIN MAXParameter Fast Mode Standard Unit MIN MAX 1 MMC/SD Electrical Data/Timing Sdclk Sdclk Sdcmd Start XmitEND Start END Video Processing Sub-System Vpss Overview Video Processing Front-End VpfeCCD Controller Ccdc Ipipe Image Pipe Sdram Hardware 3A H3A DM355-216 DM355-270 MIN MAXPclk CWE/CFIELD HD/VD11,13 12,14 CI70/YI70 CCD130 Video Processing Back-End Vpbe On-Screen Display OSD Video Encoder / Digital LCD Controller VENC/DLCD CGMS/WSS Pclk Extclk Vclkina VctlbVctl B Vdatac Vclkin a Vclk Vrefibias Iout VFBMSB 32. DAC With Buffer Circuit Tvoutv Parameter LOW Speed Full Speed High Speed Unit 10 USB10.1 USB2.0 Electrical Data/Timing Mbps Usbdm 10%V OL 90%V OHUsbdp Universal Asynchronous Receiver/Transmitter Uart Uart Electrical Data/Timing26. Timing Requirements for UARTx Receive see Figure 35. Uart Transmit/Receive Timing UARTTXDn UARTRXDn Start Bit DataBits 28. Timing Requirements for SPI All Modes1 see Figure Serial Port Interface SPISPI Electrical Data/Timing SPIxCLK ClockPolarity=0 37. SPI Master Mode External Timing Clock Phase = Spien Input Spien SpiclkSpidi Msbin Data Lsbin Spido Msbout Data Lsbout Inter-Integrated Circuit I2C SDA SCL Standard Fast Mode Unit MIN MAX13.1 I2C Electrical Data/Timing Stop Start Repeated Stop Start 34. Switching Characteristics for I2C Timings1 see FigureParameter Standard Fast Mode Unit MIN MAX Stop Audio Serial Port ASP ASP Electrical Data/Timing Otgclks Clks Clkr ClkxFSX Master Unit MIN MAX 38. ASP as SPI Switching Characteristics137. ASP as SPI Timing Requirements Parameter Master Unit MIN MAX M34 M35 M42 40. ASP as SPI Switching Characteristics139. ASP as SPI Timing Requirements M37 M38 M36 Bit0 Bitn-1 M39 M40 M43 M44 M52 42. ASP as SPI Switching Characteristics141. ASP as SPI Timing Requirements M46 M45 Bit0 Bitn-1 M49 M50 M53 M54 M62 44. ASP as SPI Switching Characteristics143. ASP as SPI Timing Requirements M56 45. Timing Requirements for Timer Input1 2 3 see Figure TimerTimer Electrical Data/Timing Timin Pulse Width Modulator PWM 16.1 PWM0/1/2/3 Electrical/Timing DataPWM0/1/2/3 48. PWM Output Delay Timing Vdccdc PWM0 Invalid PWM1 PWM2 PWM3 Valid RTO0/1/2/3 Real Time Out RTORTO Electrical/Timing Data RTO0 Ieee 1149.1 Jtag Jtag Test-Port Electrical Data/Timing 48. Timing Requirements for Jtag Test Port see FigureTCK Rtck TDO TDI TMS 52. Jtag Output Timing Rtck TDO Revision History ADDS/CHANGES/DELETES Revision History Packaging Information Thermal Resistance Characteristics Pbga Package ZCEThermal Data for ZCE ΜC/WPage Products Applications DSPRfid