Texas Instruments TMS320DM355 warranty Parameter Information Device-Specific Information

TMS320DM355

Digital Media System-on-Chip (DMSoC)

www.ti.com

SPRS463A –SEPTEMBER 2007 –REVISED SEPTEMBER 2007

5 Peripheral Information and Electrical Specifications

5.1Parameter Information Device-Specific Information

42Ω

4.0￿pF

3.5￿nH

1.85￿pF

Tester Pin￿Electronics

Transmission￿Line

Z0￿=￿50 Ω

(see￿note)

Data Sheet￿Timing￿Reference￿Point

Output

Under

Test

Device￿Pin (see￿note)

PRODUCT PREVIEW

A.The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to

add or subtract the transmission line delay (2 ns or longer) from the data sheet timings. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.

Figure 5-1. Test Load Circuit for AC Timing Measurements

The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving.

5.1.1Signal Transition Levels

All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. For 3.3 V I/O, Vref = 1.65 V. For 1.8 V I/O, Vref = 0.9 V.

Vref

Figure 5-2. Input and Output Voltage Reference Levels for AC Timing Measurements

All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOLMAX and VOH MIN for output clocks.

Vref =￿VIH MIN￿(or￿VOH MIN)

Vref =￿VIL MAX￿(or￿VOL MAX)

Figure 5-3. Rise and Fall Transition Time Voltage Reference Levels

94 Peripheral Information and Electrical Specifications Submit Documentation Feedback