Texas Instruments TMS320DM355 warranty Spien Spiclk, Spidi Msbin Data Lsbin, Input, Output

TMS320DM355

Digital Media System-on-Chip (DMSoC)

www.ti.com

SPRS463A –SEPTEMBER 2007 –REVISED SEPTEMBER 2007

SPI Master Mode Timings (Clock Phase = 1)

Table 5-31. Timing Requirements for SPI Master Mode [Clock Phase = 1] (see Figure 5-38)

NO.

13tsu(DIV-CLKL)

14tsu(DIV-CLKH)

15th(CLKL-DIV)

16th(CLKH-DIV)

Setup time, SPI_DI (input) valid before SPI_CLK (output) rising edge

Setup time, SPI_DI (in put) valid before SPI_CLK (output) falling edge

Hold time, SPI_DI (input) valid after SPI_CLK (output) rising edge

Hold time, SPI_DI (input) valid after SPI_CLK (output) falling edge

Clock Polarity = 0

Clock Polarity = 1

Clock Polarity = 0

Clock Polarity = 1

DM355	UNIT
MIN
	MAX
.5P + 3	ns
.5P + 3	ns
.5P + 3	ns
.5P + 3	ns

Table 5-32. Switching Characteristics Over Recommended Operating Conditions for SPI Master Mode

[Clock Phase = 1] (see Figure 5-38)

NO. PARAMETER

Delay time, SPI_CLK (output) falling edge to SPI_DO

DM355

UNIT

MIN MAX

(output) transition

Clock Polarity = 0

-4 5 ns

Delay time, SPI_CLK (output) rising edge to SPI_DO

(output) transition

Clock Polarity = 1

17	td(CLKL-DOV)
18	td(CLKH-DOV)
19	td(ENL-CLKH/L)
20	td(CLKL/H-DOHz)

Delay time, SPI_EN[1:0] (output) falling edge to first SPI_CLK (output) rising or falling edge

Delay time, SPI_CLK (output) falling or rising edge to SPI_DO (output) high impedance

-4	5	ns
2P+.5C	(1)	ns
(1)
P(2)	(2)	ns

(1)The delay time can be adjusted using the SPI module register C2TDELAY. See the TMS320DM355 DMSoC Serial Peripheral Interface (SPI) User'sGuide (SPRUED4).

(2)The delay time can be adjusted using the SPI module register T2CDELAY. See the TMS320DM355 DMSoC Serial Peripheral Interface (SPI) User'sGuide (SPRUED4).

PRODUCT PREVIEW

SPI_EN
SPI_CLK
(Clock￿Polarity￿=￿0)
	19
SPI_CLK
(Clock￿Polarity￿=￿1)
		15	16
	13
			14
SPI_DI	MSB￿IN		DATA	LSB￿IN
(Input)
			17	18
SPI_DO	MSB￿OUT		DATA	LSB￿OUT
(Output)

Figure 5-38. SPI Master Mode External Timing (Clock Phase = 1)

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