Texas Instruments TMS320DM355 warranty ASP as SPI Timing Requirements, M43 M44 M52

TMS320DM355

Digital Media System-on-Chip (DMSoC)

www.ti.com

SPRS463A –SEPTEMBER 2007 –REVISED SEPTEMBER 2007

Table 5-41. ASP as SPI Timing Requirements

CLKSTP = 10b, CLKXP = 1 (see Figure 5-44)

NO.			MASTER	UNIT
			MIN
				MAX
M49	tsu(DRV-CKXH)	Setup time, DR valid before CLKX high	11	ns
M50	th(CKXH-DRV)	Hold time, DR valid after CLKX high	0	ns

Table 5-42. ASP as SPI Switching Characteristics(1) (2)

CLKSTP = 10b, CLKXP = 1 (see Figure 5-44)

PRODUCT

NO.

M52 tc(CKX)

M43 td(CKXH-FXH)

M44 td(FXL-CKXL)

M45 td(CKXL-DXV)

M46 tdis(CKXH-DXHZ)

PARAMETER

Cycle time, CLKX

Delay time, CLKX high to FSX high(4)

Delay time, FSX low to CLKX low(5)

Delay time, CLKX low to DX valid

Disable time, DX high impedance following last data bit from CLKX high

MASTER		UNIT
MIN	MAX
38.5 or		ns
2P(1)(3)
T – 1	T + 3	ns
D – 2	D + 2	ns
–2	6	ns
D – 3	D + 3	ns

PREVIEW

(1)P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5) .

(2)T = CLKX period = (1 + CLKGDV) × P

C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) × P when CLKGDV is even

D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) × P when CLKGDV is even

(3)Use which ever value is greater.

(4)FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master ASP

(5)FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

CLKX
M43		M44		M52
FSX
M46			M45
DX	Bit￿0	Bit(n-1)	(n-2)	(n-3)	(n-4)
		M49	M50
DR	Bit￿0	Bit(n-1)	(n-2)	(n-3)	(n-4)

Figure 5-44. ASP as SPI: CLKSTP = 10b, CLKXP = 1

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