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Texas Instruments TMS320DM355 Aintc Interrupt Connections, Interrupt Acronym Source, Number

Models: TMS320DM355

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PRODUCT PREVIEW

TMS320DM355

Digital Media System-on-Chip (DMSoC)

www.ti.com

SPRS463A –SEPTEMBER 2007 –REVISED SEPTEMBER 2007

Table 3-1. AINTC Interrupt Connections (continued)

Interrupt	Acronym	Source	Interrupt	Acronym	Source
Number			Number
5	VPSSINT5	VPSS - INT5	37	PWMINT1	PWM 1
6	VPSSINT6	VPSS - INT6	38	PWMINT2	PWM2
7	VPSSINT7	VPSS - INT7	39	I2CINT	I2C
8	VPSSINT8	VPSS - INT8	40	UARTINT0	UART0
9	Reserved		41	UARTINT1	UART1
10	Reserved		42	SPINT0-0	SPI0
11	Reserved		43	SPINT0-1	SPI0
12	USBINT	USB OTG Collector	44	GPIO0	GPIO
13	RTOINT or	RTO or	45	GPIO1	GPIO
	TINT4	Timer 2 - TINT12
		SYS.ARM_INTMUX
14	UARTINT2 or	UART2 or	46	GPIO2	GPIO
	TINT5	Timer 2 - TINT34
15	TINT6	Timer 3 TINT12	47	GPIO3	GPIO
16	CCINT0	EDMA CC Region 0	48	GPIO4	GPIO
17	SPINT1-0 or	SPI1 or	49	GPIO5	GPIO
	CCERRINT	EDMA CC Error
18	SPINT1-1 or	SPI1 or	50	GPIO6	GPIO
	TCERRINT0	EDMA TC0 Error
19	SPINT2-0 or	SPI2 or	51	GPIO7	GPIO
	TCERRINT1	EDMA TC1 Error
20	PSCINT	PSC - ALLINT	52	GPIO8	GPIO
21	SPINT2-1	SPI2	53	GPIO9	GPIO
22	TINT7	Timer3 - TINT34	54	GPIOBNK0	GPIO
23	SDIOINT0	MMC/SD0	55	GPIOBNK1	GPIO
24	MBXINT0 or	ASP0 or	56	GPIOBNK2	GPIO
	MBXINT1	ASP1
25	MBRINT0 or	ASP0 or	57	GPIOBNK3	GPIO
	MBRINT1	ASP1
26	MMCINT0	MMC/SD0	58	GPIOBNK4	GPIO
27	MMCINT1	MMC/SC1	59	GPIOBNK5	GPIO
28	PWMINT3	PWM3	60	GPIOBNK6	GPIO
29	DDRINT	DDR EMIF	61	COMMTX	ARMSS
30	AEMIFINT	Async EMIF	62	COMMRX	ARMSS
31	SDIOINT1	SDIO1	63	EMUINT	E2ICE

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Detailed Device Description

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Texas Instruments TMS320DM355 warranty Aintc Interrupt Connections, Interrupt Acronym Source, Number

Contents

Features TMS320DM355 Digital Media System-on-Chip DMSoCTMS320DM355 Digital Media System-on-Chip DMSoC Description Functional Block Diagram Functional Block DiagramContents ARM926EJ-S Risc CPUDevice Characteristics Characteristics of the ProcessorHardware Features DM355DM355 ARM Configuration Bus Access to Peripherals Memory Map SummaryDM355 Memory Map Edma USBAddress Pin Assignments Pin Map Bottom ViewPin Map Quadrant B Pin Map Quadrant C Pin Map Quadrant D CCD Controller Signals for Each Input Mode Pin FunctionsImage Data Input Video Processing Front End PIN Name CCDCCD Controller/Video Input Terminal Functions Terminal Name noType DescriptionImage Data Output Video Processing Back End Vpbe CamhdCamvd Camwen FIELD\ R5 GIO083 PCLK/ T3 GIO082Signals for Vpbe Display Modes PIN NameYCC8 Prgb Srgb REC656Digital Video Terminal Functions Terminal NameAsynchronous External Memory Interface Aemif Analog Video Terminal FunctionsAsynchronous EMIF/NAND/OneNAND Terminal Functions TerminalType 1 Other 2 ZvddEMBA1 EMBA0DDR Memory Interface 10. DDR Terminal FunctionsDDRDQ14 DDRDQ13DDRDQ12 DDRDQ11Gpio 11. Gpio Terminal FunctionsUART2R MMCSD1 UART2C MMCSD1ASP0FS ASP0CLAsync Emif Data Bus bit01 GIO039 J17 Type 1 Other 2 3 Description PWM3B COUT1PWM1 COUT7 RTO0 COUT6Camwe Nfield / R5 GIO083 Camvd SPI2SDE SPI2SDISPI0SDI Multi-Media Card/Secure Digital MMC/SD Interfaces 12. MMC/SD Terminal FunctionsUniversal Serial Bus USB Interface Audio Interfaces13. USB Terminal Functions 14. ASP Terminal FunctionsUart Interface 15. Uart Terminal Functions10 I2C Interface Serial Interface16. I2C Terminal Functions 17. SPI Terminal FunctionsClock Interface 18. Clocks Terminal FunctionsReal Time Output RTO Interface Pulse Width Modulator PWM Interface19. RTO Terminal Functions 20. PWM Terminal FunctionsSystem Configuration Interface 21. System/Boot Terminal FunctionsPWM3B Field PWM3DEmulation 22. Emulation Terminal Functions23. DM355 Pin Descriptions Pin ListBGA GIO M4 I/O CcdcPINMUX08.CIN32 PINMUX09.CIN10R3 I/O Ccdc Camhd Ccdc Camvd CcdcCamwenfie Ccdc PINMUX011.CAMPWM2A / RTO0 PWM2B / RTO1PWM2C / RTO2 PWM2D / RTO3Reset Description Mux Control Name BGA Type Group Reset DescriptionState PWR Ddri GND DdrdPWR Ddrd Ddrzn Ddri AemiAECFG1 GIO GroupAECFG0 GIO GIO EMIF2 PINMUX21.EMA0PINMUX24.EMD1 PINMUX26.EMCE PINMUX25.EMD7PINMUX27.EMCE PINMUX28.EMW EOE GIOPINMUX29.EMW AIT GIOMMCSD1DAT MMCSD1 DATA3 PINMUX398.GIO2UART2RTS GIO Uart UART2 RTS MMCSD1DATPINMUX324.GIO1 GIO SPI1SDENA1PINMUX327.GIO8 PINMUX328.GIO7Usbvbus Usbp Usbdrvvbu UsbpGND Usbp PWR UsbpReset ASP1CLKXASP1FSX ASP1CLKRCvdd RSV03 RSV04 RSV05 RSV06 RSV07Type Group Cvdd PWR K10 Device Support Development ToolsDevice Nomenclature Software Development ToolsDevice Documentation Related Documentation From Texas InstrumentsProduct Preview SPRUF71 ARM Subsystem Overview Components of the ARM SubsystemARM926EJ-S Risc CPU 2 MMU 1 CP15Caches and Write Buffer Tightly Coupled Memory TCM Advanced High-performance Bus AHBEmbedded Trace Macrocell ETM and Embedded Trace Buffer ETB Memory MappingExternal Memories PeripheralsARM Interrupt Controller Aintc Interrupt MappingInterrupt Acronym Source Aintc Interrupt ConnectionsNumber Device Clocking OverviewPreview Supported Clocking Configurations for DM355-216 Vpss VCO ARMPlldiv Syscl Sysclk PLLDIV3 PLLDIV4 Supported Clocking Configurations for DM355-270 PredMpeg and Jpeg PLLDIV1 Sysc Plldi SYSCLK2 PLLDIV3 Sysclk PLLDIV4 SYSCLK4Postdi Prediv PllmPlldiv Sysc SYSCLK2 PLLDIV3 Syscl PLLDIV4 SYSCLK4 Video Processing Back End Clocking Peripheral Clocking ConsiderationsUSB Clocking Product Preview PLL Controller Pllc PLL Controller ModulePLLC1 10. PLLC1 Output ClocksPLLC1 Configuration In DM355 TMS320DM355PLLC2 Configuration in DM355 PLLC211. PLLC2 Output Clocks SYSCLK1 DDR PHYPower and Sleep Controller PSC System Control ModulePin Multiplexing Hardware Controlled Pin Multiplexing12. Peripheral Pin Mux Overview Peripheral Muxed With Primary Function Secondary FunctionDevice Reset 13. Aecfg Async Emif Configuration Pin Mux Coding14. Reset Types Software Controlled Pin MultiplexingDefault Device Configurations Device Configuration Pins15. Device Configuration Device Configuration AffectedPLL Configuration Power Domain and Module State ConfigurationDefault States 16. Module ConfigurationModule Aemif Configuration ARM Boot Mode ConfigurationDevice Boot Modes Boot Modes Overview Power Management Boot Mode Functional Block Diagram17. Power Management Features Power Management Features Description14 64-Bit Crossbar Architecture Crossbar ConnectionsEdma Controller 18. Crossbar Connection MatrixProduct Preview 19. Edma Channel Synchronization Events1 Edma Channel Synchronization EventsEdma Event Name Event Description Channel MPEG/JPEG Overview 19. Edma Channel Synchronization EventsDevice Operating Conditions VbusRecommended Operating Conditions MIN NOM MAX UnitCV DD USB UsbvbusTest Conditions ParameterMIN TYP MAX Unit Signal Transition Levels Parameter Information Device-Specific InformationTester PinElectronics Output Under TestTiming Parameters and Board Routing Analysis Recommended Clock and Control Signal Transition Behavior Power SuppliesPower Supplies Tolerance PackagePower-Supply Design Considerations Power-Supply SequencingPower-Supply Decoupling Reset Reset Electrical Data/TimingTiming Requirements for Reset 1 2 see Figure MINOscillators and Clocks 1 MXI1 24-MHz Oscillator2 MXI2 27-MHz Oscillator optional oscillator Parameter MIN TYP MAX UnitESR MXI2 MXO2Clock PLL Electrical Data/Timing Input and Output Clocks Timing Requirements for MXI1/CLKIN11 2 see FigureMIN TYP MAX MXI/CLKINUNI MXI/CLKIN CLKOUT111. CLKOUT3 Timing General-Purpose Input/Output Gpio Gpio Peripheral Input/Output Electrical Data/Timing10. Timing Requirements for Gpio Inputs see Figure MIN Unit MAXGPIx GPOx Gpio Peripheral External Interrupts Electrical Data/TimingEXTINTx External Memory Interface Emif Asynchronous Emif AemifNand NAND, SmartMedia, xD OneNANDWrites ReadsMAX T DM355 MINNom RST*EUNI MAX T WS+WST+WH*E WS+WST+WH+EWOutput hold time, Emwe high to WH*E EMD150 invalid EMCE10 EMA130Emoe EMD150Emoe Emwait EMA130 EMD150Emwe Emwait 18. Synchronous OneNAND Flash Read Timing 2 DDR2 Memory Controller 2.1 DDR2/mDDR Memory Controller Electrical Data/TimingFast Mode Standard Mode Unit MIN MAX Parameter Fast Mode Standard Unit MIN MAXMMC/SD 1 MMC/SD Electrical Data/TimingSdclk Sdcmd Start Xmit ENDSdclk Start ENDVideo Processing Front-End Vpfe Video Processing Sub-System Vpss OverviewCCD Controller Ccdc Ipipe Image Pipe SdramHardware 3A H3A MIN MAX DM355-216 DM355-270Pclk HD/VD 11,13 12,14CWE/CFIELD CI70/YI70 CCD130Video Processing Back-End Vpbe On-Screen Display OSDVideo Encoder / Digital LCD Controller VENC/DLCD CGMS/WSSPclk Extclk MINVctlb VclkinaVctl B Vdatac Vclkin a VclkIout VFB VrefibiasMSB 32. DAC With Buffer Circuit Tvoutv10 USB 10.1 USB2.0 Electrical Data/TimingParameter LOW Speed Full Speed High Speed Unit Mbps10%V OL 90%V OH UsbdmUsbdp Uart Electrical Data/Timing Universal Asynchronous Receiver/Transmitter Uart26. Timing Requirements for UARTx Receive see Figure 35. Uart Transmit/Receive Timing UARTTXDn UARTRXDn Start Bit DataBitsSerial Port Interface SPI SPI Electrical Data/Timing28. Timing Requirements for SPI All Modes1 see Figure SPIxCLK ClockPolarity=037. SPI Master Mode External Timing Clock Phase = SpienSpien Spiclk Spidi Msbin Data LsbinInput Spido Msbout Data LsboutInter-Integrated Circuit I2C Standard Fast Mode Unit MIN MAX 13.1 I2C Electrical Data/TimingSDA SCL Stop Start Repeated34. Switching Characteristics for I2C Timings1 see Figure Parameter Standard Fast Mode Unit MIN MAXStop Start StopAudio Serial Port ASP ASP Electrical Data/Timing OtgclksClkx Clks ClkrFSX 38. ASP as SPI Switching Characteristics1 37. ASP as SPI Timing RequirementsMaster Unit MIN MAX Parameter Master Unit MIN MAX40. ASP as SPI Switching Characteristics1 39. ASP as SPI Timing RequirementsM34 M35 M42 M37 M38 M36 Bit0 Bitn-1 M39 M4042. ASP as SPI Switching Characteristics1 41. ASP as SPI Timing RequirementsM43 M44 M52 M46 M45 Bit0 Bitn-1 M49 M5044. ASP as SPI Switching Characteristics1 43. ASP as SPI Timing RequirementsM53 M54 M62 M56Timer Timer Electrical Data/Timing45. Timing Requirements for Timer Input1 2 3 see Figure Timin16.1 PWM0/1/2/3 Electrical/Timing Data Pulse Width Modulator PWMPWM0/1/2/3 48. PWM Output Delay Timing Vdccdc PWM0 Invalid PWM1 PWM2 PWM3 ValidReal Time Out RTO RTO Electrical/Timing DataRTO0/1/2/3 RTO0Ieee 1149.1 Jtag 48. Timing Requirements for Jtag Test Port see Figure Jtag Test-Port Electrical Data/TimingTCK Rtck TDO TDI TMS 52. Jtag Output Timing Rtck TDORevision History ADDS/CHANGES/DELETESRevision History Thermal Resistance Characteristics Pbga Package ZCE Thermal Data for ZCEPackaging Information ΜC/WPage DSP Products ApplicationsRfid