Texas Instruments TMS320DM355 warranty DM355-216 DM355-270, Min Max, Pclk

PRODUCT

TMS320DM355

Digital Media System-on-Chip (DMSoC)

www.ti.com

SPRS463A –SEPTEMBER 2007 –REVISED SEPTEMBER 2007

5.9.1.4 VPFE Electrical Data/Timing

Table 5-17. Timing Requirements for VPFE PCLK Master/Slave Mode (see Figure 5-23)

NO.			DM355-216		DM355-270		UNIT
			MIN	MAX	MIN	MAX
1	t	Cycle time, PCLK(1)	18.52	100	14.81	100	ns
	c(PCLK)
2	tw(PCLKH)	Pulse duration, PCLK high	5.7		5.7		ns
3	tw(PCLKL)	Pulse duration, PCLK low	5.7		5.7		ns
4	tt(PCLK)	Transition time, PCLK		3		3	ns

(1)The PCLK frequency must be less than or equal to half the VPSS clock frequency—i.e., PCLK ≤ SYSCLK4/2.

2 3

1

PCLK

4

4

Figure 5-23. VPFE PCLK Timing

Table 5-18. Timing Requirements for VPFE (CCD) Slave Mode (see Figure 5-24)

PREVIEW

NO.

5tsu(CCDV-PCLK)

6th(PCLK-CCDV)

7tsu(HDV-PCLK)

8th(PCLK-HDV)

9tsu(VDV-PCLK)

10th(PCLK-VDV)

11tsu(C_WEV-PCLK)

12th(PCLK-C_WEV)

13tsu(C_FIELDV-PCLK)

14th(PCLK-C_FIELDV)

	DM355	UNIT
	MIN
		MAX
Setup time, CCD valid before PCLK edge	3	ns
Hold time, CCD valid after PCLK edge	2	ns
Setup time, HD valid before PCLK edge	3	ns
Hold time, HD valid after PCLK edge	2	ns
Setup time, VD valid before PCLK edge	3	ns
Hold time, VD valid after PCLK edge	2	ns
Setup time, C_WE valid before PCLK edge	3	ns
Hold time, C_WE valid after PCLK edge	2	ns
Setup time, C_FIELD valid before PCLK edge	3	ns
Hold time, C_FIELD valid after PCLK edge	2	ns

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