Texas Instruments TMS320DM355 warranty

Contents

Main 1 TMS320DM355 Digital Media System-on-Chip (DMSoC) 1.1 Features Page 1.2 Description TMS320DM355Digital Media System-on-Chip (DMSoC) 1.3 Functional Block Diagram BufferLogic TMS320DM355 Digital Media System-on-Chip (DMSoC)4Submit Documentation Feedback SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Figure 1-1 shows the functional block diagram of the DM355 device. TMS320DM355Digital Media System-on-Chip (DMSoC) 2 Device Overview 2.1 Device Characteristics 2.2 Memory Map Summary Table 2-3. DM355 ARM Configuration Bus Access to Peripherals Table 2-3. DM355 ARM Configuration Bus Access to Peripherals (continued) 2.3 Pin Assignments 2.3.1 Pin Map (Bottom View) Submit Documentation Feedback Device Overview 9 Figure 2-1. Pin Map [Quadrant A] Figure 2-2. Pin Map [Quadrant B] Device Overview10 Submit Documentation Feedback Figure 2-3. Pin Map [Quadrant C] Submit Documentation Feedback Device Overview 11 Figure 2-4. Pin Map [Quadrant D] 12 Device Overview Submit Documentation Feedback 2.4 Pin Functions 2.4.1 Image Data Input - Video Processing Front End Table 2-5. CCD Controller/Video Input Terminal Functions 2.4.2 Image Data Output - Video Processing Back End (VPBE) Table 2-5. CCD Controller/Video Input Terminal Functions (continued) Table 2-6. Signals for VPBE Display Modes Table 2-7. Digital Video Terminal Functions 2.4.3 Asynchronous External Memory Interface (AEMIF) Table 2-8. Analog Video Terminal Functions Table 2-9. Asynchronous EMIF/NAND/OneNAND Terminal Functions (continued) 2.4.4 DDR Memory Interface TMS320DM355 Table 2-9. Asynchronous EMIF/NAND/OneNAND Terminal Functions (continued) The DDR EMIF supports DDR2 and mobile DDR. Table 2-10. DDR Terminal Functions Table 2-10. DDR Terminal Functions (continued) 2.4.5 GPIO Page Page Page Page Page 2.4.6 Multi-Media Card/Secure Digital (MMC/SD) Interfaces 2.4.7 Universal Serial Bus (USB) Interface 2.4.8 Audio Interfaces 2.4.9 UART Interface Table 2-14. ASP Terminal Functions (continued) 2.4.10 I C Interface The includes an I 2.4.11 Serial Interface Table 2-15. UART Terminal Functions (continued) TMS320DM355 Table 2-17. SPI Terminal Functions (continued) The provides interface with the system clocks. Table 2-18. Clocks Terminal Functions 2.4.13 Real Time Output (RTO) Interface 2.4.14 Pulse Width Modulator (PWM) Interface The provides Real Time Output (RTO) interface. Table 2-19. RTO Terminal Functions The provides Pulse Width Modulator (PWM) interface. Table 2-20. PWM Terminal Functions 2.4.15 System Configuration Interface Table 2-20. PWM Terminal Functions (continued) 2.4.16 Emulation TMS320DM355Digital Media System-on-Chip (DMSoC) Table 2-21. System/Boot Terminal Functions (continued) 2.5 Pin List Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page 2.6 Device Support 2.6.1 Development Tools 2.6.2 Device Nomenclature TMS320DM355Digital Media System-on-Chip (DMSoC) 2.6.3 Device Documentation Page Page 3 Detailed Device Description 3.1 ARM Subsystem Overview 3.1.1 Components of the ARM Subsystem 3.2 ARM926EJ-S RISC CPU 3.2.1 CP15 3.2.2 MMU 3.2.3 Caches and Write Buffer Page 3.3.2 External Memories 3.3.3 Peripherals 3.4 ARM Interrupt Controller (AINTC) 3.4.1 Interrupt Mapping Table 3-1. AINTC Interrupt Connections (continued) Page UART0,1 Sequencer Figure 3-2. Device Clocking Block Diagram 66 Detailed Device Description Submit Documentation Feedback 3.5.2 Supported Clocking Configurations for DM355-216 Page 3.5.3 Supported Clocking Configurations for DM355-270 Table 3-7. PLL2 Supported Clocking Configurations for DM355-270 (24 MHz reference) (continued) 3.5.4 Peripheral Clocking Considerations Page 3.6 PLL Controller (PLLC) 3.6.1 PLL Controller Module 3.6.2 PLLC1 Figure 3-3. PLLC1 Configuration In DM355 Submit Documentation Feedback Detailed Device Description 75 3.6.3 PLLC2 3.7 Power and Sleep Controller (PSC) 3.8 System Control Module 3.9 Pin Multiplexing 3.9.1 Hardware Controlled Pin Multiplexing 3.9.2 Software Controlled Pin Multiplexing 3.10 Device Reset Table 3-13. AECFG (Async EMIF Configuration) Pin Mux Coding 3.11 Default Device Configurations 3.11.1 Device Configuration Pins Page Table 3-16. Module Configuration 3.11.4 ARM Boot Mode Configuration 3.11.5 AEMIF Configuration 3.12 Device Boot Modes 3.12.1 Boot Modes Overview 3.13 Power Management Page 3.14 64-Bit Crossbar Architecture 3.14.1 Crossbar Connections 3.14.2 EDMA Controller Page Table 3-19. EDMA Channel Synchronization Events 3.15 MPEG/JPEG Overview Table 3-19. EDMA Channel Synchronization Events (continued) 4 Device Operating Conditions 4.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted) 4.2 Recommended Operating Conditions 4.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted) 5 Peripheral Information and Electrical Specifications 5.1 Parameter Information Device-Specific Information 5.1.1 Signal Transition Levels Page 5.2 Recommended Clock and Control Signal Transition Behavior 5.3 Power Supplies All clocks and control signals should transition between V and V (or between V and V 5.3.1 Power-Supply Sequencing 5.4 Reset 5.4.1 Reset Electrical Data/Timing Table 5-2. Timing Requirements for Reset (see Figure 5-4 ) Figure 5-4. Reset Timing 5.5 Oscillators and Clocks 5.5.1 MXI1 (24-MHz) Oscillator 5.5.2 MXI2 (27-MHz) Oscillator (optional oscillator) 5.5.3 Clock PLL Electrical Data/Timing (Input and Output Clocks) Table 5-5. Timing Requirements for MXI1/CLKIN1 (see Figure 5-7 ) Figure 5-7. MXI1/CLKIN1 Timing Table 5-6. Timing Requirements for MXI2/CLKIN2 (see Figure 5-7 ) Table 5-7. Switching Characteristics Over Recommended Operating Conditions for CLKOUT1 (seeFigure 5-9 ) (seeFigure 5-10 ) Figure 5-10. CLKOUT2 Timing Table 5-9. Switching Characteristics Over Recommended Operating Conditions for CLKOUT3 (seeFigure 5-11 ) Figure 5-11. CLKOUT3 Timing 5.6 General-Purpose Input/Output (GPIO) 5.6.1 GPIO Peripheral Input/Output Electrical Data/Timing 5.6.2 GPIO Peripheral External Interrupts Electrical Data/Timing Figure 5-12. GPIO Port Timing Table 5-12. Timing Requirements for External Interrupts/EDMA Events (see Figure 5-13 ) Figure 5-13. GPIO External Interrupt Timing 5.7 External Memory Interface (EMIF) 5.7.1 Asynchronous EMIF (AEMIF) (see Figure 5-14and Figure 5-15 ) (see Figure 5-14 and Figure 5-15 ) Page DM355 UNINO. PARAMETER TMIN Nom MAX Output hold time, EM_WE high to27 t Submit Documentation Feedback Peripheral Information and Electrical Specifications 109 (WH)*E nsEM_D[15:0] invalid Figure 5-14. Asynchronous Memory Read Timing for EMIF Figure 5-15. Asynchronous Memory Write Timing for EMIF Figure 5-16. EM_WAIT Read Timing Requirements Figure 5-17. EM_WAIT Write Timing Requirements Figure 5-18. Synchronous OneNAND Flash Read Timing 5.7.2 DDR2 Memory Controller 5.8 MMC/SD 5.8.1 MMC/SD Electrical Data/Timing Figure 5-19. MMC/SD Host Command Timing Figure 5-20. MMC/SD Card Response Timing Figure 5-21. MMC/SD Host Write Timing Figure 5-22. MMC/SD Host Read and Card CRC Status Timing 5.9 Video Processing Sub-System (VPSS) Overview 5.9.1 Video Processing Front-End (VPFE) Page Page Page (see Figure 5-25 ) Figure 5-25. VPFE (CCD) Master Mode Input Data Timing 5.9.2 Video Processing Back-End (VPBE) Page (seeFigure 5-28 ) (see Figure 5-29 ) Figure 5-29. VPBE Control and Data Output With Respect to PCLK and EXTCLK (see Figure 5-30 ) Figure 5-31. DAC Only Application Example Submit Documentation Feedback Peripheral Information and Electrical Specifications 125 Figure 5-32. DAC With Buffer Circuit 5.10 USB 2.0 5.10.1 USB2.0 Electrical Data/Timing Figure 5-33. USB2.0 Integrated Transceiver Interface Timing Figure 5-34. USB Reference Resistor Routing 5.11 Universal Asynchronous Receiver/Transmitter (UART) 5.11.1 UART Electrical Data/Timing Figure 5-35. UART Transmit/Receive Timing 5.12 Serial Port Interface (SPI) 5.12.1 SPI Electrical Data/Timing (see Figure 5-37 ) Figure 5-37. SPI Master Mode External Timing (Clock Phase = 0) Figure 5-38. SPI Master Mode External Timing (Clock Phase = 1) 5.13 Inter-Integrated Circuit (I2C) 5.13.1 I2C Electrical Data/Timing 5.13.1.1 Inter-Integrated Circuits (I2C) Timing Table 5-33. Timing Requirements for I2C Timings (see Figure 5-39 ) Figure 5-39. I2C Receive Timings Table 5-34. Switching Characteristics for I2C Timings (see Figure 5-40 ) CAUTIONThe DM355 I C pins use a standard 4-mA LVCMOS buffer, not the slow I/OP bufferdefined in the I C specification. Series resistors may be necessary to reduce noise atthe system level. 5.14 Audio Serial Port (ASP) 5.14.1 ASP Electrical Data/Timing 5.14.1.1 Audio Serial Port (ASP) Timing Table 5-35. Timing Requirements for ASP (see Figure 5-41 ) Table 5-36. Switching Characteristics Over Recommended Operating Conditions for ASP (see Figure 5-41 ) Figure 5-41. ASP Timing Table 5-37. ASP as SPI Timing Requirements CLKSTP = 10b, CLKXP = 0 (see Figure 5-42 ) Table 5-38. ASP as SPI Switching Characteristics CLKSTP = 10b, CLKXP = 0 (see Figure 5-42 ) Figure 5-42. ASP as SPI: CLKSTP = 10b, CLKXP = 0 Table 5-39. ASP as SPI Timing Requirements CLKSTP = 11b, CLKXP = 0 Table 5-40. ASP as SPI Switching Characteristics CLKSTP = 11b, CLKXP = 0 (see Figure 5-43 ) Figure 5-43. ASP as SPI: CLKSTP = 11b, CLKXP = 0 Table 5-41. ASP as SPI Timing Requirements CLKSTP = 10b, CLKXP = 1 (see Figure 5-44 ) Table 5-42. ASP as SPI Switching Characteristics CLKSTP = 10b, CLKXP = 1 (see Figure 5-44 ) Figure 5-44. ASP as SPI: CLKSTP = 10b, CLKXP = 1 Table 5-43. ASP as SPI Timing Requirements CLKSTP = 11b, CLKXP = 1 (see Figure 5-45 ) Table 5-44. ASP as SPI Switching Characteristics CLKSTP = 11b, CLKXP = 1 (see Figure 5-45 ) Figure 5-45. ASP as SPI: CLKSTP = 11b, CLKXP = 1 5.15 Timer 5.15.1 Timer Electrical Data/Timing 5.16 Pulse Width Modulator (PWM) 5.16.1 PWM0/1/2/3 Electrical/Timing Data Figure 5-48. PWM Output Delay Timing 5.17 Real Time Out (RTO) 5.17.1 RTO Electrical/Timing Data Figure 5-49. RTO Output Timing Figure 5-50. RTO Output Delay Timing 5.18 IEEE 1149.1 JTAG 5.18.1 JTAG Test-Port Electrical Data/Timing Table 5-48. Timing Requirements for JTAG Test Port (see Figure 5-51 ) Figure 5-51. JTAG Input Timing Figure 5-52. JTAG Output Timing 6 Revision History Page 7 Mechanical Data 7.1 Thermal Data for ZCE 7.1.1 Packaging Information Page IMPORTANT NOTICE