Texas Instruments TMS320DM355 Video Processing Sub-System Vpss Overview, CCD Controller Ccdc

TMS320DM355

Digital Media System-on-Chip (DMSoC)

www.ti.com

SPRS463A –SEPTEMBER 2007 –REVISED SEPTEMBER 2007

5.9 Video Processing Sub-System (VPSS) Overview

The contains a Video Processing Sub-System (VPSS) that provides an input interface (Video Processing Front End or VPFE) for external imaging peripherals such as image sensors, video decoders, etc.; and an output interface (Video Processing Back End or VPBE) for display devices, such as analog SDTV displays, digital LCD panels, HDTV video encoders, etc.

In addition to these peripherals, there is a set of common buffer memory and DMA control to ensure efficient use of the DDR2 burst bandwidth. The shared buffer logic/memory is a unique block that is tailored for seamlessly integrating the VPSS into an image/video processing system. It acts as the primary source or sink to all the VPFE and VPBE modules that are either requesting or transferring data from/to DDR2. In order to efficiently utilize the external DDR2 bandwidth, the shared buffer logic/memory interfaces with the DMA system via a high bandwidth bus (64-bit wide). The shared buffer logic/memory also interfaces with all the VPFE and VPBE modules via a 128-bit wide bus. The shared buffer logic/memory (divided into the read & write buffers and arbitration logic) is capable of performing the following functions. It is imperative that the VPSS utilize DDR2 bandwidth efficiently due to both its large bandwidth requirements and the real-time requirements of the VPSS modules. Because it is possible to configure the VPSS modules in such a way that DDR2 bandwidth is exceeded, a set of user accessible registers is provided to monitor overflows or failures in data transfers.

5.9.1Video Processing Front-End (VPFE)

The VPFE or Video Processing Front-End block is comprised of the CCD Controller (CCDC), Image Pipe (IPIPE), and Hardware 3A Statistic Generator (H3A). These modules are described in the sections that follow.

5.9.1.1 CCD Controller (CCDC)

The CCDC is responsible for accepting raw (unprocessed) image/video data from a sensor (CMOS or CCD). In addition, the CCDC can accept YUV video data in numerous formats, typically from so-called video decoder devices. In the case of raw inputs, the CCDC output requires additional image processing to transform the raw input image to the final processed image. This processing can be done either on-the-fly in the Preview Engine hardware ISP or in software on the ARM and MPEG/JPEG co-processor subsystems. In parallel, raw data input to the CCDC can also used for computing various statistics (3A, Histogram) to eventually control the image/video tuning parameters. The CCDC is programmed via control and parameter registers. DM355 performance is enhanced by its dedicated hard-wired MPEG/JPEG co-processor (MJCP). The MJCP performs all the computational operations required for JPE and MPEG4 compression. These operations can be invoked using the xDM (xDIAS for Digital Media) APIs. For more information, refer to the xDIAS-DM (xDIAS for Digital Media) User's Guide (SPRUEC8). The following features are supported by the CCDC module.

∙Support for conventional Bayer pattern.

∙Generates HD/VD timing signals and field ID to an external timing generator or can synchronize to the external timing generator.

∙Support for progressive and interlaced sensors (hardware support for up to 2 fields and firmware support for higher number of fields, typically 3-, 4-, and 5-field sensors).

∙Support for up to 67.5 MHz sensor clock (270-MHz speed grade device)

∙Support for REC656/CCIR-656 standard (YCbCr 422 format, either 8- or 16-bit).

∙Support for YCbCr 422 format, either 8- or 16-bit with discrete H and VSYNC signals.

∙Support for up to 14-bit input.

∙Support for color space conversion

∙Generates optical black clamping signals.

∙Support for shutter signal control.

∙Support for digital clamping and black level compensation.

∙Fault pixel correction based on a lookup table that contains row and column position of the pixel to be corrected.

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