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Texas Instruments TMS320DM355 warranty Vclkina, Vctlb, Vctl B Vdatac

Models: TMS320DM355

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TMS320DM355

Digital Media System-on-Chip (DMSoC)

www.ti.com

SPRS463A –SEPTEMBER 2007 –REVISED SEPTEMBER 2007

VCLKIN(A)

(Positive Edge Clocking)

VCLKIN(A)

(Negative Edge Clocking)

10

9

VCTL(B)

A.VCLKIN=PCLKorEXTCLK

B.VCTL=HSYNC,VSYNC,andFIELD

Figure 5-28. VPBE Input Timing With Respect to PCLK and EXTCLK

Table 5-23. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and

Data Output With Respect to PCLK and EXTCLK(1) (2) (3) (see Figure 5-29)

NO.		PARAMETER	DM355		UNIT
NO.		PARAMETER	MIN	MAX	UNIT
			MIN	MAX
11	td(VCLKIN-VCTLV)	Delay time, VCLKIN edge to VCTL valid		13.3	ns
12	td(VCLKIN-VCTLIV)	Delay time, VCLKIN edge to VCTL invalid	2		ns
13	td(VCLKIN-VDATAV)	Delay time, VCLKIN edge to VDATA valid		13.3	ns
14	td(VCLKIN-VDATAIV)	Delay time, VCLKIN edge to VDATA invalid	2		ns

(1)The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising edge of VCLKIN is referenced. When in negative edge clocking mode, the falling edge of VCLKIN is referenced.

(2)VCLKIN = PCLK or EXTCLK

(3)VCTL = HSYNC, VSYNC, FIELD, and LCD_OE

VCLKIN(A)

(Positive Edge Clocking)

VCLKIN(A)

(Negative Edge Clocking)

11	12
VCTL(B)
13	14

VDATA(C)

PRODUCT PREVIEW

A.VCLKIN=PCLKorEXTCLK

B.VCTL=HSYNC,VSYNC,FIELD,andLCD_OE

C.VDATA=COUT[7:0],YOUT[7:0],R[7:3],G[7:2],andB[7:3]

Figure 5-29. VPBE Control and Data Output With Respect to PCLK and EXTCLK

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Peripheral Information and Electrical Specifications

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Texas Instruments TMS320DM355 warranty Vclkina, Vctlb, Vctl B Vdatac

Contents

TMS320DM355 Digital Media System-on-Chip DMSoC FeaturesTMS320DM355 Digital Media System-on-Chip DMSoC Description Functional Block Diagram Functional Block DiagramARM926EJ-S Risc CPU ContentsDM355 Device CharacteristicsCharacteristics of the Processor Hardware FeaturesEdma USB DM355 ARM Configuration Bus Access to PeripheralsMemory Map Summary DM355 Memory MapAddress Pin Map Bottom View Pin AssignmentsPin Map Quadrant B Pin Map Quadrant C Pin Map Quadrant D PIN Name CCD CCD Controller Signals for Each Input ModePin Functions Image Data Input Video Processing Front EndDescription CCD Controller/Video Input Terminal FunctionsTerminal Name no TypeCamwen FIELD\ R5 GIO083 PCLK/ T3 GIO082 Image Data Output Video Processing Back End VpbeCamhd CamvdREC656 Signals for Vpbe Display ModesPIN Name YCC8 Prgb SrgbTerminal Name Digital Video Terminal FunctionsTerminal Asynchronous External Memory Interface AemifAnalog Video Terminal Functions Asynchronous EMIF/NAND/OneNAND Terminal FunctionsEMBA0 Type 1 Other 2Zvdd EMBA110. DDR Terminal Functions DDR Memory InterfaceDDRDQ11 DDRDQ14DDRDQ13 DDRDQ1211. Gpio Terminal Functions GpioASP0CL UART2R MMCSD1UART2C MMCSD1 ASP0FSAsync Emif Data Bus bit01 GIO039 J17 PWM3B COUT1 Type 1 Other 2 3 DescriptionRTO0 COUT6 PWM1 COUT7Camwe Nfield / R5 GIO083 Camvd SPI2SDI SPI2SDESPI0SDI 12. MMC/SD Terminal Functions Multi-Media Card/Secure Digital MMC/SD Interfaces14. ASP Terminal Functions Universal Serial Bus USB InterfaceAudio Interfaces 13. USB Terminal Functions15. Uart Terminal Functions Uart Interface17. SPI Terminal Functions 10 I2C InterfaceSerial Interface 16. I2C Terminal Functions18. Clocks Terminal Functions Clock Interface20. PWM Terminal Functions Real Time Output RTO InterfacePulse Width Modulator PWM Interface 19. RTO Terminal FunctionsPWM3D System Configuration Interface21. System/Boot Terminal Functions PWM3B Field22. Emulation Terminal Functions EmulationPin List 23. DM355 Pin DescriptionsBGA PINMUX09.CIN10 GIOM4 I/O Ccdc PINMUX08.CIN32R3 I/O Ccdc PINMUX011.CAM Camhd CcdcCamvd Ccdc Camwenfie CcdcPWM2D / RTO3 PWM2A / RTO0PWM2B / RTO1 PWM2C / RTO2Reset Description Mux Control Reset Description Name BGA Type GroupState Aemi PWR DdriGND Ddrd PWR Ddrd Ddrzn DdriGroup AECFG1 GIOAECFG0 GIO PINMUX21.EMA0 GIO EMIF2PINMUX24.EMD1 PINMUX25.EMD7 PINMUX26.EMCEPINMUX27.EMCE AIT GIO PINMUX28.EMWEOE GIO PINMUX29.EMWUART2 RTS MMCSD1DAT MMCSD1DATMMCSD1 DATA3 PINMUX398.GIO2 UART2RTS GIO UartPINMUX328.GIO7 PINMUX324.GIO1GIO SPI1SDENA1 PINMUX327.GIO8PWR Usbp Usbvbus UsbpUsbdrvvbu Usbp GND UsbpASP1CLKR ResetASP1CLKX ASP1FSXRSV03 RSV04 RSV05 RSV06 RSV07 CvddType Group Cvdd PWR K10 Software Development Tools Device SupportDevelopment Tools Device NomenclatureRelated Documentation From Texas Instruments Device DocumentationProduct Preview SPRUF71 Components of the ARM Subsystem ARM Subsystem OverviewARM926EJ-S Risc CPU 1 CP15 2 MMUCaches and Write Buffer Memory Mapping Tightly Coupled Memory TCMAdvanced High-performance Bus AHB Embedded Trace Macrocell ETM and Embedded Trace Buffer ETBInterrupt Mapping External MemoriesPeripherals ARM Interrupt Controller AintcAintc Interrupt Connections Interrupt Acronym SourceNumber Overview Device ClockingPreview Supported Clocking Configurations for DM355-216 ARM Vpss VCOPlldiv Syscl Sysclk PLLDIV3 PLLDIV4 PLLDIV1 Sysc Plldi SYSCLK2 PLLDIV3 Sysclk PLLDIV4 SYSCLK4 Supported Clocking Configurations for DM355-270Pred Mpeg and JpegPrediv Pllm PostdiPlldiv Sysc SYSCLK2 PLLDIV3 Syscl PLLDIV4 SYSCLK4 Peripheral Clocking Considerations Video Processing Back End ClockingUSB Clocking Product Preview PLL Controller Module PLL Controller Pllc10. PLLC1 Output Clocks PLLC1TMS320DM355 PLLC1 Configuration In DM355SYSCLK1 DDR PHY PLLC2 Configuration in DM355PLLC2 11. PLLC2 Output ClocksSystem Control Module Power and Sleep Controller PSCPeripheral Muxed With Primary Function Secondary Function Pin MultiplexingHardware Controlled Pin Multiplexing 12. Peripheral Pin Mux OverviewSoftware Controlled Pin Multiplexing Device Reset13. Aecfg Async Emif Configuration Pin Mux Coding 14. Reset TypesDevice Configuration Affected Default Device ConfigurationsDevice Configuration Pins 15. Device ConfigurationPower Domain and Module State Configuration PLL Configuration16. Module Configuration Default StatesModule ARM Boot Mode Configuration Aemif ConfigurationDevice Boot Modes Boot Modes Overview Boot Mode Functional Block Diagram Power ManagementPower Management Features Description 17. Power Management Features18. Crossbar Connection Matrix 14 64-Bit Crossbar ArchitectureCrossbar Connections Edma ControllerProduct Preview Edma Channel Synchronization Events 19. Edma Channel Synchronization Events1Edma Event Name Event Description Channel 19. Edma Channel Synchronization Events MPEG/JPEG OverviewVbus Device Operating ConditionsUSB Usbvbus Recommended Operating ConditionsMIN NOM MAX Unit CV DDParameter Test ConditionsMIN TYP MAX Unit Output Under Test Signal Transition LevelsParameter Information Device-Specific Information Tester PinElectronicsTiming Parameters and Board Routing Analysis Tolerance Package Recommended Clock and Control Signal Transition BehaviorPower Supplies Power SuppliesPower-Supply Sequencing Power-Supply Design ConsiderationsPower-Supply Decoupling MIN ResetReset Electrical Data/Timing Timing Requirements for Reset 1 2 see Figure1 MXI1 24-MHz Oscillator Oscillators and ClocksMXI2 MXO2 2 MXI2 27-MHz Oscillator optional oscillatorParameter MIN TYP MAX Unit ESRMXI/CLKIN Clock PLL Electrical Data/Timing Input and Output ClocksTiming Requirements for MXI1/CLKIN11 2 see Figure MIN TYP MAXMXI/CLKIN CLKOUT1 UNI11. CLKOUT3 Timing MIN Unit MAX General-Purpose Input/Output GpioGpio Peripheral Input/Output Electrical Data/Timing 10. Timing Requirements for Gpio Inputs see FigureGpio Peripheral External Interrupts Electrical Data/Timing GPIx GPOxEXTINTx OneNAND External Memory Interface EmifAsynchronous Emif Aemif Nand NAND, SmartMedia, xDReads WritesMAX T WS+WST+WH*E WS+WST+WH+EW DM355 MINNomRST*E UNI MAX TEMD150 Output hold time, Emwe high to WH*E EMD150 invalid EMCE10EMA130 EmoeEMA130 EMD150 Emoe EmwaitEmwe Emwait 18. Synchronous OneNAND Flash Read Timing 2.1 DDR2/mDDR Memory Controller Electrical Data/Timing 2 DDR2 Memory Controller1 MMC/SD Electrical Data/Timing Fast Mode Standard Mode Unit MIN MAXParameter Fast Mode Standard Unit MIN MAX MMC/SDStart END Sdclk Sdcmd Start XmitEND SdclkVideo Processing Sub-System Vpss Overview Video Processing Front-End VpfeCCD Controller Ccdc Sdram Ipipe Image PipeHardware 3A H3A DM355-216 DM355-270 MIN MAXPclk CI70/YI70 CCD130 HD/VD11,13 12,14 CWE/CFIELDOn-Screen Display OSD Video Processing Back-End VpbeCGMS/WSS Video Encoder / Digital LCD Controller VENC/DLCDMIN Pclk ExtclkVclkina VctlbVctl B Vdatac Vclk Vclkin aVrefibias Iout VFBMSB Tvoutv 32. DAC With Buffer CircuitMbps 10 USB10.1 USB2.0 Electrical Data/Timing Parameter LOW Speed Full Speed High Speed UnitUsbdm 10%V OL 90%V OHUsbdp Universal Asynchronous Receiver/Transmitter Uart Uart Electrical Data/Timing26. Timing Requirements for UARTx Receive see Figure UARTTXDn UARTRXDn Start Bit DataBits 35. Uart Transmit/Receive TimingSPIxCLK ClockPolarity=0 Serial Port Interface SPISPI Electrical Data/Timing 28. Timing Requirements for SPI All Modes1 see FigureSpien 37. SPI Master Mode External Timing Clock Phase =Spido Msbout Data Lsbout Spien SpiclkSpidi Msbin Data Lsbin InputInter-Integrated Circuit I2C Stop Start Repeated Standard Fast Mode Unit MIN MAX13.1 I2C Electrical Data/Timing SDA SCLStop 34. Switching Characteristics for I2C Timings1 see FigureParameter Standard Fast Mode Unit MIN MAX Stop StartAudio Serial Port ASP Otgclks ASP Electrical Data/TimingClks Clkr ClkxFSX Parameter Master Unit MIN MAX 38. ASP as SPI Switching Characteristics137. ASP as SPI Timing Requirements Master Unit MIN MAXM37 M38 M36 Bit0 Bitn-1 M39 M40 40. ASP as SPI Switching Characteristics139. ASP as SPI Timing Requirements M34 M35 M42M46 M45 Bit0 Bitn-1 M49 M50 42. ASP as SPI Switching Characteristics141. ASP as SPI Timing Requirements M43 M44 M52M56 44. ASP as SPI Switching Characteristics143. ASP as SPI Timing Requirements M53 M54 M62Timin TimerTimer Electrical Data/Timing 45. Timing Requirements for Timer Input1 2 3 see FigurePulse Width Modulator PWM 16.1 PWM0/1/2/3 Electrical/Timing DataPWM0/1/2/3 Vdccdc PWM0 Invalid PWM1 PWM2 PWM3 Valid 48. PWM Output Delay TimingRTO0 Real Time Out RTORTO Electrical/Timing Data RTO0/1/2/3Ieee 1149.1 Jtag Jtag Test-Port Electrical Data/Timing 48. Timing Requirements for Jtag Test Port see FigureTCK Rtck TDO TDI TMS Rtck TDO 52. Jtag Output TimingADDS/CHANGES/DELETES Revision HistoryRevision History ΜC/W Thermal Resistance Characteristics Pbga Package ZCEThermal Data for ZCE Packaging InformationPage Products Applications DSPRfid