Texas Instruments TMS320DM355 warranty DDR Memory Interface, DDR Terminal Functions

TMS320DM355

Digital Media System-on-Chip (DMSoC)

www.ti.com

SPRS463A –SEPTEMBER 2007 –REVISED SEPTEMBER 2007

Table 2-9. Asynchronous EMIF/NAND/OneNAND Terminal Functions (continued)

PRODUCT

TERMINAL		TYPE (1)	OTHER (2) (3)
NAME	NO.
EM_CE0/	J16	I/O/Z	VDD
GIO037
EM_CE1/	G19	I/O/Z	VDD
GIO036
EM_WE/	J15	I/O/Z	VDD
GIO035
EM_OE/	F19	I/O/Z	VDD
GIO034
EM_WAIT/	G18	I/O/Z	VDD
GIO033
EM_ADV/	H16	I/O/Z	VDD
GIO032
EM_CLK/	E19	I/O/Z	VDD
GIO031

DESCRIPTION

Async EMIF: Lowest numbered chip select. Can be programmed to be used for

standard asynchronous memories (example: flash), OneNAND, or NAND memory. Used for the default boot and ROM boot modes.

GIO: GIO[037]

Async EMIF: Second chip select. Can be programmed to be used for standard

asynchronous memories(example: flash), OneNAND, or NAND memory.

GIO: GIO[036]

Async EMIF: Write Enable

NAND/SM/xD: WE (Write Enable) output

GIO: GIO[035]

Async EMIF: Output Enable

NAND/SM/xD: RE (Read Enable) output

GIO: GIO[034]

Async EMIF: Async WAIT

NAND/SM/xD: RDY/ BSY input

GIO: GIO[033]

OneNAND: Address valid detect for OneNAND interface

GIO: GIO[032]

OneNAND: Clock for OneNAND flash interface

GIO: GIO[031]

PREVIEW

2.4.4DDR Memory Interface

The DDR EMIF supports DDR2 and mobile DDR.

Table 2-10. DDR Terminal Functions

TERMINAL		TYPE (1)	OTHER (2) (3)
NAME	NO.
DDR_CLK	W9	I/O/Z	VDD_DDR
DDR_CLK	W8	I/O/Z	VDD_DDR
DDR_RAS	T6	I/O/Z	VDD_DDR
DDR_CAS	V9	I/O/Z	VDD_DDR
DDR_WE	W10	I/O/Z	VDD_DDR
DDR_CS	T8	I/O/Z	VDD_DDR
DDR_CKE	V10	I/O/Z	VDD_DDR
DDR_DQM[	U15	I/O/Z	VDD_DDR
1]
DDR_DQM[	T12	I/O/Z	VDD_DDR
0]
DDR_DQS[	V15	I/O/Z	VDD_DDR
1]
DDR_DQS[	V12	I/O/Z	VDD_DDR
0]
DDR_BA[2]	V8	I/O/Z	VDD_DDR
DDR_BA[1]	U7	I/O/Z	VDD_DDR
DDR_BA[0]	U8	I/O/Z	VDD_DDR
DDR_A13	U6	I/O/Z	VDD_DDR
DDR_A12	V7	I/O/Z	VDD_DDR
DDR_A11	W7	I/O/Z	VDD_DDR

DESCRIPTION

DDR Data Clock

DDR Complementary Data Clock

DDR Row Address Strobe

DDR Column Address Strobe

DDR Write Enable

DDR Chip Select

DDR Clock Enable

Data mask outputs:

∙DQM0 - For DDR_DQ[7:0]

∙DQM1 - For DDR_DQ[15:8]

Data strobe input/outputs for each byte of the 16-bit data bus used to synchronize the data transfers. Output to DDR when writing and inputs when reading.

∙DQS1 - For DDR_DQ[15:8]

∙DQS0 - For DDR_DQ[7:0]

Bank select outputs. Two are required for 1Gb DDR2 memories. Bank select outputs. Two are required for 1Gb DDR2 memories. Bank select outputs. Two are required for 1Gb DDR2 memories.

DDR Address Bus bit 13

DDR Address Bus bit 12

DDR Address Bus bit 11

(1)I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2)Specifies the operating I/O supply voltage for each signal. See Section 5.3, Power Supplies for more detail.

(3)PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)

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