Texas Instruments TMS320DM355 warranty Vclkin a

TMS320DM355

Digital Media System-on-Chip (DMSoC)

www.ti.com

SPRS463A –SEPTEMBER 2007 –REVISED SEPTEMBER 2007

Table 5-24. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and

Data Output With Respect to VCLK(1) (2) (see Figure 5-30)

NO.

17 tc(VCLK)

18 tw(VCLKH)

19 tw(VCLKL)

20 tt(VCLK)

21td(VCLKINH-VCLKH)

22td(VCLKINL-VCLKL)

23td(VCLK-VCTLV)

24td(VCLK-VCTLIV)

25td(VCLK-VDATAV)

26td(VCLK-VDATAIV)

PARAMETER	DM355		UNIT
	MIN	MAX
Cycle time, VCLK	13.33	160	ns
Pulse duration, VCLK high	5.7		ns
Pulse duration, VCLK low	5.7		ns
Transition time, VCLK		3	ns
Delay time, VCLKIN high to VCLK high	2	12	ns
Delay time, VCLKIN low to VCLK low	2	12	ns
Delay time, VCLK edge to VCTL valid		4	ns
Delay time, VCLK edge to VCTL invalid	0		ns
Delay time, VCLK edge to VDATA valid		4	ns
Delay time, VCLK edge to VDATA invalid	0		ns

PRODUCT PREVIEW

(1)The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising edge of VCLK is referenced. When in negative edge clocking mode, the falling edge of VCLK is referenced.

(2)VCLKIN = PCLK or EXTCLK. Note that if the CCDC is used, the PCLK frequency must be less than or equal to half the VPSS clock frequency—i.e., PCLK ≤ SYSCLK4/2.

VCLKIN(A)
21	22	17	19	18
VCLK
(Positive Edge
Clocking)
VCLK
(Negative Edge
Clocking)	23	24	20	20
VCTL(B)
	25	26

VDATA(C)

A.VCLKIN￿=￿PCLK￿or￿EXTCLK

B.VCTL￿=￿HSYNC,￿VSYNC,￿FIELD,￿and￿LCD_OE

C.VDATA￿￿=￿COUT[7:0],￿YOUT[7:0],￿R[7:3],￿G[7:2],￿and￿B[7:3]

Figure 5-30. VPBE Control and Data Output Timing With Respect to VCLK

5.9.2.4 DAC and Video Buffer Electrical Data/Timing

The DAC and video buffer can be configured in a DAC only configuration or in a DAC and video buffer configuration. In the DAC only configuration the internal video buffer is not used and an external video buffer is attached to the DAC. In the DAC and video buffer configuration, the DAC and internal video buffer are both used and a TV cable may be attached directly to the output of the video buffer. See Figure 5-31and Figure 5-32for recommenced circuits for each configuration.

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