Texas Instruments TMS320DM355 DDRDQ14, DDRDQ13, DDRDQ12, DDRDQ11, DDRDQ10, DDRDQ09, DDRDQ08

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TMS320DM355

Digital Media System-on-Chip (DMSoC)

SPRS463A –SEPTEMBER 2007 –REVISED SEPTEMBER 2007

Table 2-10. DDR Terminal Functions (continued)

TERMINAL		TYPE (1)
NAME	NO.
DDR_A10	V6	I/O/Z
DDR_A09	W6	I/O/Z
DDR_A08	W5	I/O/Z
DDR_A07	V5	I/O/Z
DDR_A06	U5	I/O/Z
DDR_A05	W4	I/O/Z
DDR_A04	V4	I/O/Z
DDR_A03	W3	I/O/Z
DDR_A02	W2	I/O/Z
DDR_A01	V3	I/O/Z
DDR_A00	V2	I/O/Z
DDR_DQ15	W17	I/O/Z
DDR_DQ14	V16	I/O/Z
DDR_DQ13	W16	I/O/Z
DDR_DQ12	U16	I/O/Z
DDR_DQ11	W15	I/O/Z
DDR_DQ10	W14	I/O/Z
DDR_DQ09	V14	I/O/Z
DDR_DQ08	U13	I/O/Z
DDR_DQ07	W13	I/O/Z
DDR_DQ06	V13	I/O/Z
DDR_DQ05	W12	I/O/Z
DDR_DQ04	U12	I/O/Z
DDR_DQ03	T11	I/O/Z
DDR_DQ02	U11	I/O/Z
DDR_DQ01	W11	I/O/Z
DDR_DQ00	V11	I/O/Z
DDR_GATE	W18	I/O/Z
0
DDR_GATE	V17	I/O/Z
1
DDR_VREF	U10	I/O/Z
VSSA_DLL	R11	I/O/Z
VDDA33_DDR	R10	I/O/Z
DLL
DDR_ZN	T9	I/O/Z

OTHER (2) (3)

VDD_DDR

VDD_DDR

VDD_DDR

VDD_DDR

VDD_DDR

VDD_DDR

VDD_DDR

VDD_DDR

VDD_DDR

VDD_DDR

VDD_DDR

VDD_DDR

VDD_DDR

VDD_DDR

VDD_DDR

VDD_DDR

VDD_DDR

VDD_DDR

VDD_DDR

VDD_DDR

VDD_DDR

VDD_DDR

VDD_DDR

VDD_DDR

VDD_DDR

VDD_DDR

VDD_DDR

VDD_DDR

VDD_DDR

VDD_DDR

VDD_DDR

VDD_DDR

VDD_DDR

DESCRIPTION

DDR Address Bus bit 10

DDR Address Bus bit 09

DDR Address Bus bit 08

DDR Address Bus bit 07

DDR Address Bus bit 06

DDR Address Bus bit 05

DDR Address Bus bit 04

DDR Address Bus bit 03

DDR Address Bus bit 02

DDR Address Bus bit 01

DDR Address Bus bit 00

DDR Data Bus bit 15

DDR Data Bus bit 14

DDR Data Bus bit 13

DDR Data Bus bit 12

DDR Data Bus bit 11

DDR Data Bus bit 10

DDR Data Bus bit 09

DDR Data Bus bit 08

DDR Data Bus bit 07

DDR Data Bus bit 06

DDR Data Bus bit 05

DDR Data Bus bit 04

DDR Data Bus bit 03

DDR Data Bus bit 02

DDR Data Bus bit 01

DDR Data Bus bit 00

DDR: Loopback signal for external DQS gating. Route to DDR and back to DDR_GATE0 with same constraints as used for DDR clock and data.

DDR: Loopback signal for external DQS gating. Route to DDR and back to DDR_GATE0 with same constraints as used for DDR clock and data.

DDR: Voltage input for the SSTL_18 I/O buffers. Note even in the case of mDDR an external resistor divider connected to this pin is necessary.

DDR: Ground for the DDR DLL

DDR: Power (3.3 V) for the DDR DLL

DDR: Reference output for drive strength calibration of N and P channel outputs. Tie to ground via 50 ohm resistor @ 0.5% tolerance.

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