PLLC1 Configuration In DM355 | Texas Instruments TMS320DM355

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CLKMODE

CLKIN 1

OSCIN 0

				TMS320DM355
			Digital Media System-on-Chip (DMSoC)
			SPRS463A –SEPTEMBER 2007 –REVISED SEPTEMBER 2007
			PLLEN
Pre-DIV	PLL	Post-DIV	1	SYSCLK1
(/8)		(/2or/1)		SYSCLK1
				(ARMandMPEG/JPEG

			PLLDIV1(/2)
			PLLDIV1(/2)	Coprocessor)
			0	Coprocessor)
			0	SYSCLK2
	PLLM		PLLDIV2(/4)	SYSCLK2
	PLLM		PLLDIV2(/4)	(peripherals)
	(programmable)			(peripherals)
	(programmable)			SYSCLK3
			PLLDIV3(/3)	SYSCLK3
			PLLDIV3(/3)	(VPBE)
				(VPBE)
			PLLDIV4	SYSCLK4
			(/4or/2)	(VPSS)
				AUXCLK
				(Peripherals,
				CLKOUT1)
				PRODUCTPREVIEW
			BPDIV(/3)	SYSCLKBP
				(CLKOUT2)
	Figure 3-3. PLLC1 Configuration In DM355

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Detailed Device Description

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Texas Instruments TMS320DM355 warranty PLLC1 Configuration In DM355

TMS320DM355 specifications

The Texas Instruments TMS320DM355 is a versatile digital signal processor designed to support a wide array of multimedia applications, specifically in the realms of digital video and audio processing. As part of the TMS320 family of digital signal processors, the DM355 brings a blend of computational power, energy efficiency, and integrated features that make it highly effective for tasks such as video encoding, decoding, and general signal processing.

One of the standout features of the DM355 is its advanced DaVinci architecture, which is specifically optimized for multimedia tasks. This architecture integrates both DSP and application processing functionalities. The dual-core architecture includes a high-performance DSP core that specializes in real-time signal processing alongside an ARM926EJ-S RISC microprocessor, facilitating the execution of complex algorithms and control tasks.

The DM355 offers robust multimedia processing capabilities with support for several video formats, including MPEG-2, MPEG-4, H.264, and JPEG. This enables developers to create powerful video applications for a variety of devices, from industrial systems to consumer electronics. Its processing capabilities extend to audio processing, allowing it to efficiently handle audio codecs and enhance audio quality in applications ranging from IP cameras to set-top boxes.

In terms of connectivity, the TMS320DM355 supports various interfaces including USB 2.0, Ethernet, and various serial interfaces like UART, SPI, and I2C. This wide range of connectivity options ensures that the DM355 can easily interface with different peripherals and network components, making it a suitable choice for networked applications.

Energy efficiency is another significant advantage of the DM355. With a focus on low power consumption, the device is designed to operate effectively in battery-powered and heat-sensitive environments. Its low thermal design power allows for extended operational life and reduced thermal management requirements, making it ideal for portable devices.

Furthermore, the DM355 is supported by a comprehensive software development framework, including the TI Code Composer Studio and a range of middleware tools, which streamline application development and speed up time to market. Its rich ecosystem enhances its usability across different applications, ensuring that developers can leverage the full potential of the hardware.

In summary, the Texas Instruments TMS320DM355 stands out as a powerful yet cost-effective DSP solution, combining advanced multimedia processing capabilities, robust connectivity options, and energy efficiency. Its unique architecture and extensive support resources make it a preferred choice for developers seeking to create innovative multimedia solutions.

Contents

TMS320DM355 Digital Media System-on-Chip DMSoC Features TMS320DM355 Digital Media System-on-Chip DMSoC Description Functional Block Diagram Functional Block Diagram ARM926EJ-S Risc CPU Contents DM355 Device CharacteristicsCharacteristics of the Processor Hardware Features Edma USB DM355 ARM Configuration Bus Access to PeripheralsMemory Map Summary DM355 Memory Map Address Pin Map Bottom View Pin Assignments Pin Map Quadrant B Pin Map Quadrant C Pin Map Quadrant D PIN Name CCD CCD Controller Signals for Each Input ModePin Functions Image Data Input Video Processing Front End Description CCD Controller/Video Input Terminal FunctionsTerminal Name no Type Camwen FIELD\ R5 GIO083 PCLK/ T3 GIO082 Image Data Output Video Processing Back End VpbeCamhd Camvd REC656 Signals for Vpbe Display ModesPIN Name YCC8 Prgb Srgb Terminal Name Digital Video Terminal Functions Terminal Asynchronous External Memory Interface AemifAnalog Video Terminal Functions Asynchronous EMIF/NAND/OneNAND Terminal Functions EMBA0 Type 1 Other 2Zvdd EMBA1 10. DDR Terminal Functions DDR Memory Interface DDRDQ11 DDRDQ14DDRDQ13 DDRDQ12 11. Gpio Terminal Functions Gpio ASP0CL UART2R MMCSD1UART2C MMCSD1 ASP0FS Async Emif Data Bus bit01 GIO039 J17 PWM3B COUT1 Type 1 Other 2 3 Description RTO0 COUT6 PWM1 COUT7Camwe Nfield / R5 GIO083 Camvd SPI2SDI SPI2SDESPI0SDI 12. MMC/SD Terminal Functions Multi-Media Card/Secure Digital MMC/SD Interfaces 14. ASP Terminal Functions Universal Serial Bus USB InterfaceAudio Interfaces 13. USB Terminal Functions 15. Uart Terminal Functions Uart Interface 17. SPI Terminal Functions 10 I2C InterfaceSerial Interface 16. I2C Terminal Functions 18. Clocks Terminal Functions Clock Interface 20. PWM Terminal Functions Real Time Output RTO InterfacePulse Width Modulator PWM Interface 19. RTO Terminal Functions PWM3D System Configuration Interface21. System/Boot Terminal Functions PWM3B Field 22. Emulation Terminal Functions Emulation Pin List 23. DM355 Pin DescriptionsBGA PINMUX09.CIN10 GIOM4 I/O Ccdc PINMUX08.CIN32 R3 I/O Ccdc PINMUX011.CAM Camhd CcdcCamvd Ccdc Camwenfie Ccdc PWM2D / RTO3 PWM2A / RTO0PWM2B / RTO1 PWM2C / RTO2 Reset Description Mux Control Reset Description Name BGA Type GroupState Aemi PWR DdriGND Ddrd PWR Ddrd Ddrzn Ddri Group AECFG1 GIOAECFG0 GIO PINMUX21.EMA0 GIO EMIF2PINMUX24.EMD1 PINMUX25.EMD7 PINMUX26.EMCEPINMUX27.EMCE AIT GIO PINMUX28.EMWEOE GIO PINMUX29.EMW UART2 RTS MMCSD1DAT MMCSD1DATMMCSD1 DATA3 PINMUX398.GIO2 UART2RTS GIO Uart PINMUX328.GIO7 PINMUX324.GIO1GIO SPI1SDENA1 PINMUX327.GIO8 PWR Usbp Usbvbus UsbpUsbdrvvbu Usbp GND Usbp ASP1CLKR ResetASP1CLKX ASP1FSX RSV03 RSV04 RSV05 RSV06 RSV07 CvddType Group Cvdd PWR K10 Software Development Tools Device SupportDevelopment Tools Device Nomenclature Related Documentation From Texas Instruments Device Documentation Product Preview SPRUF71 Components of the ARM Subsystem ARM Subsystem Overview ARM926EJ-S Risc CPU 1 CP15 2 MMUCaches and Write Buffer Memory Mapping Tightly Coupled Memory TCMAdvanced High-performance Bus AHB Embedded Trace Macrocell ETM and Embedded Trace Buffer ETB Interrupt Mapping External MemoriesPeripherals ARM Interrupt Controller Aintc Aintc Interrupt Connections Interrupt Acronym SourceNumber Overview Device Clocking Preview Supported Clocking Configurations for DM355-216 ARM Vpss VCOPlldiv Syscl Sysclk PLLDIV3 PLLDIV4 PLLDIV1 Sysc Plldi SYSCLK2 PLLDIV3 Sysclk PLLDIV4 SYSCLK4 Supported Clocking Configurations for DM355-270Pred Mpeg and Jpeg Prediv Pllm PostdiPlldiv Sysc SYSCLK2 PLLDIV3 Syscl PLLDIV4 SYSCLK4 Peripheral Clocking Considerations Video Processing Back End ClockingUSB Clocking Product Preview PLL Controller Module PLL Controller Pllc 10. PLLC1 Output Clocks PLLC1 TMS320DM355 PLLC1 Configuration In DM355 SYSCLK1 DDR PHY PLLC2 Configuration in DM355PLLC2 11. PLLC2 Output Clocks System Control Module Power and Sleep Controller PSC Peripheral Muxed With Primary Function Secondary Function Pin MultiplexingHardware Controlled Pin Multiplexing 12. Peripheral Pin Mux Overview Software Controlled Pin Multiplexing Device Reset13. Aecfg Async Emif Configuration Pin Mux Coding 14. Reset Types Device Configuration Affected Default Device ConfigurationsDevice Configuration Pins 15. Device Configuration Power Domain and Module State Configuration PLL Configuration 16. Module Configuration Default StatesModule ARM Boot Mode Configuration Aemif ConfigurationDevice Boot Modes Boot Modes Overview Boot Mode Functional Block Diagram Power Management Power Management Features Description 17. Power Management Features 18. Crossbar Connection Matrix 14 64-Bit Crossbar ArchitectureCrossbar Connections Edma Controller Product Preview Edma Channel Synchronization Events 19. Edma Channel Synchronization Events1Edma Event Name Event Description Channel 19. Edma Channel Synchronization Events MPEG/JPEG Overview Vbus Device Operating Conditions USB Usbvbus Recommended Operating ConditionsMIN NOM MAX Unit CV DD Parameter Test ConditionsMIN TYP MAX Unit Output Under Test Signal Transition LevelsParameter Information Device-Specific Information Tester PinElectronics Timing Parameters and Board Routing Analysis Tolerance Package Recommended Clock and Control Signal Transition BehaviorPower Supplies Power Supplies Power-Supply Sequencing Power-Supply Design ConsiderationsPower-Supply Decoupling MIN ResetReset Electrical Data/Timing Timing Requirements for Reset 1 2 see Figure 1 MXI1 24-MHz Oscillator Oscillators and Clocks MXI2 MXO2 2 MXI2 27-MHz Oscillator optional oscillatorParameter MIN TYP MAX Unit ESR MXI/CLKIN Clock PLL Electrical Data/Timing Input and Output ClocksTiming Requirements for MXI1/CLKIN11 2 see Figure MIN TYP MAX MXI/CLKIN CLKOUT1 UNI 11. CLKOUT3 Timing MIN Unit MAX General-Purpose Input/Output GpioGpio Peripheral Input/Output Electrical Data/Timing 10. Timing Requirements for Gpio Inputs see Figure Gpio Peripheral External Interrupts Electrical Data/Timing GPIx GPOxEXTINTx OneNAND External Memory Interface EmifAsynchronous Emif Aemif Nand NAND, SmartMedia, xD Reads WritesMAX T WS+WST+WH*E WS+WST+WH+EW DM355 MINNomRST*E UNI MAX T EMD150 Output hold time, Emwe high to WH*E EMD150 invalid EMCE10EMA130 Emoe EMA130 EMD150 Emoe EmwaitEmwe Emwait 18. Synchronous OneNAND Flash Read Timing 2.1 DDR2/mDDR Memory Controller Electrical Data/Timing 2 DDR2 Memory Controller 1 MMC/SD Electrical Data/Timing Fast Mode Standard Mode Unit MIN MAXParameter Fast Mode Standard Unit MIN MAX MMC/SD Start END Sdclk Sdcmd Start XmitEND Sdclk Video Processing Sub-System Vpss Overview Video Processing Front-End VpfeCCD Controller Ccdc Sdram Ipipe Image Pipe Hardware 3A H3A DM355-216 DM355-270 MIN MAXPclk CI70/YI70 CCD130 HD/VD11,13 12,14 CWE/CFIELD On-Screen Display OSD Video Processing Back-End Vpbe CGMS/WSS Video Encoder / Digital LCD Controller VENC/DLCD Pclk Extclk Vclkina VctlbVctl B Vdatac Vclk Vclkin a Vrefibias Iout VFBMSB Tvoutv 32. DAC With Buffer Circuit Mbps 10 USB10.1 USB2.0 Electrical Data/Timing Parameter LOW Speed Full Speed High Speed Unit Usbdm 10%V OL 90%V OHUsbdp Universal Asynchronous Receiver/Transmitter Uart Uart Electrical Data/Timing26. Timing Requirements for UARTx Receive see Figure UARTTXDn UARTRXDn Start Bit DataBits 35. Uart Transmit/Receive Timing SPIxCLK ClockPolarity=0 Serial Port Interface SPISPI Electrical Data/Timing 28. Timing Requirements for SPI All Modes1 see Figure Spien 37. SPI Master Mode External Timing Clock Phase = Spido Msbout Data Lsbout Spien SpiclkSpidi Msbin Data Lsbin Input Inter-Integrated Circuit I2C Stop Start Repeated Standard Fast Mode Unit MIN MAX13.1 I2C Electrical Data/Timing SDA SCL Stop 34. Switching Characteristics for I2C Timings1 see FigureParameter Standard Fast Mode Unit MIN MAX Stop Start Audio Serial Port ASP Otgclks ASP Electrical Data/Timing Clks Clkr ClkxFSX Parameter Master Unit MIN MAX 38. ASP as SPI Switching Characteristics137. ASP as SPI Timing Requirements Master Unit MIN MAX M37 M38 M36 Bit0 Bitn-1 M39 M40 40. ASP as SPI Switching Characteristics139. ASP as SPI Timing Requirements M34 M35 M42 M46 M45 Bit0 Bitn-1 M49 M50 42. ASP as SPI Switching Characteristics141. ASP as SPI Timing Requirements M43 M44 M52 M56 44. ASP as SPI Switching Characteristics143. ASP as SPI Timing Requirements M53 M54 M62 Timin TimerTimer Electrical Data/Timing 45. Timing Requirements for Timer Input1 2 3 see Figure Pulse Width Modulator PWM 16.1 PWM0/1/2/3 Electrical/Timing DataPWM0/1/2/3 Vdccdc PWM0 Invalid PWM1 PWM2 PWM3 Valid 48. PWM Output Delay Timing RTO0 Real Time Out RTORTO Electrical/Timing Data RTO0/1/2/3 Ieee 1149.1 Jtag Jtag Test-Port Electrical Data/Timing 48. Timing Requirements for Jtag Test Port see FigureTCK Rtck TDO TDI TMS Rtck TDO 52. Jtag Output Timing ADDS/CHANGES/DELETES Revision History Revision History ΜC/W Thermal Resistance Characteristics Pbga Package ZCEThermal Data for ZCE Packaging InformationPage Products Applications DSPRfid

TMS320DM355

Digital Media System-on-Chip (DMSoC)

Figure 3-3. PLLC1 Configuration In DM355

TMS320DM355 specifications