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Texas Instruments TMS320DM355 warranty Inter-Integrated Circuit I2C

Models: TMS320DM355

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PRODUCT PREVIEW

TMS320DM355

Digital Media System-on-Chip (DMSoC)

www.ti.com

SPRS463A –SEPTEMBER 2007 –REVISED SEPTEMBER 2007

5.13 Inter-Integrated Circuit (I2C)

The inter-integrated circuit (I2C) module provides an interface between and other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an I2C-bus. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the DM355 through the I2C module.

The I2C port supports:

∙Compatible with Philips I2C Specification Revision 2.1 (January 2000)

∙Fast Mode up to 400 Kbps (no fail-safe I/O buffers)

∙Noise Filter to Remove Noise 50 ns or less

∙Seven- and Ten-Bit Device Addressing Modes

∙Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality

∙Events: DMA, Interrupt, or Polling

∙Slew-Rate Limited Open-Drain Output Buffers

For more detailed information on the I2C peripheral, see the Documentation Support section for the Inter-Integrated Circuit (I2C) Module Reference Guide.

134

Peripheral Information and Electrical Specifications

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Texas Instruments TMS320DM355 warranty Inter-Integrated Circuit I2C

Contents

Features TMS320DM355 Digital Media System-on-Chip DMSoCTMS320DM355 Digital Media System-on-Chip DMSoC Description Functional Block Diagram Functional Block DiagramContents ARM926EJ-S Risc CPUHardware Features Device CharacteristicsCharacteristics of the Processor DM355DM355 Memory Map DM355 ARM Configuration Bus Access to PeripheralsMemory Map Summary Edma USBAddress Pin Assignments Pin Map Bottom ViewPin Map Quadrant B Pin Map Quadrant C Pin Map Quadrant D Image Data Input Video Processing Front End CCD Controller Signals for Each Input ModePin Functions PIN Name CCDType CCD Controller/Video Input Terminal FunctionsTerminal Name no DescriptionCamvd Image Data Output Video Processing Back End VpbeCamhd Camwen FIELD\ R5 GIO083 PCLK/ T3 GIO082YCC8 Prgb Srgb Signals for Vpbe Display ModesPIN Name REC656Digital Video Terminal Functions Terminal NameAsynchronous EMIF/NAND/OneNAND Terminal Functions Asynchronous External Memory Interface AemifAnalog Video Terminal Functions TerminalEMBA1 Type 1 Other 2Zvdd EMBA0DDR Memory Interface 10. DDR Terminal FunctionsDDRDQ12 DDRDQ14DDRDQ13 DDRDQ11Gpio 11. Gpio Terminal FunctionsASP0FS UART2R MMCSD1UART2C MMCSD1 ASP0CLAsync Emif Data Bus bit01 GIO039 J17 Type 1 Other 2 3 Description PWM3B COUT1Camwe Nfield / R5 GIO083 Camvd RTO0 COUT6PWM1 COUT7 SPI0SDI SPI2SDISPI2SDE Multi-Media Card/Secure Digital MMC/SD Interfaces 12. MMC/SD Terminal Functions13. USB Terminal Functions Universal Serial Bus USB InterfaceAudio Interfaces 14. ASP Terminal FunctionsUart Interface 15. Uart Terminal Functions16. I2C Terminal Functions 10 I2C InterfaceSerial Interface 17. SPI Terminal FunctionsClock Interface 18. Clocks Terminal Functions19. RTO Terminal Functions Real Time Output RTO InterfacePulse Width Modulator PWM Interface 20. PWM Terminal FunctionsPWM3B Field System Configuration Interface21. System/Boot Terminal Functions PWM3DEmulation 22. Emulation Terminal FunctionsBGA Pin List23. DM355 Pin Descriptions PINMUX08.CIN32 GIOM4 I/O Ccdc PINMUX09.CIN10R3 I/O Ccdc Camwenfie Ccdc Camhd CcdcCamvd Ccdc PINMUX011.CAMPWM2C / RTO2 PWM2A / RTO0PWM2B / RTO1 PWM2D / RTO3Reset Description Mux Control State Reset DescriptionName BGA Type Group PWR Ddrd Ddrzn Ddri PWR DdriGND Ddrd AemiAECFG0 GIO GroupAECFG1 GIO PINMUX24.EMD1 PINMUX21.EMA0GIO EMIF2 PINMUX27.EMCE PINMUX25.EMD7PINMUX26.EMCE PINMUX29.EMW PINMUX28.EMWEOE GIO AIT GIOUART2RTS GIO Uart MMCSD1DATMMCSD1 DATA3 PINMUX398.GIO2 UART2 RTS MMCSD1DATPINMUX327.GIO8 PINMUX324.GIO1GIO SPI1SDENA1 PINMUX328.GIO7GND Usbp Usbvbus UsbpUsbdrvvbu Usbp PWR UsbpASP1FSX ResetASP1CLKX ASP1CLKRType Group RSV03 RSV04 RSV05 RSV06 RSV07Cvdd Cvdd PWR K10 Device Nomenclature Device SupportDevelopment Tools Software Development ToolsDevice Documentation Related Documentation From Texas InstrumentsProduct Preview SPRUF71 ARM Subsystem Overview Components of the ARM SubsystemARM926EJ-S Risc CPU Caches and Write Buffer 1 CP152 MMU Embedded Trace Macrocell ETM and Embedded Trace Buffer ETB Tightly Coupled Memory TCMAdvanced High-performance Bus AHB Memory MappingARM Interrupt Controller Aintc External MemoriesPeripherals Interrupt MappingNumber Aintc Interrupt ConnectionsInterrupt Acronym Source Device Clocking OverviewPreview Supported Clocking Configurations for DM355-216 Plldiv Syscl Sysclk PLLDIV3 PLLDIV4 ARMVpss VCO Mpeg and Jpeg Supported Clocking Configurations for DM355-270Pred PLLDIV1 Sysc Plldi SYSCLK2 PLLDIV3 Sysclk PLLDIV4 SYSCLK4Plldiv Sysc SYSCLK2 PLLDIV3 Syscl PLLDIV4 SYSCLK4 Prediv PllmPostdi USB Clocking Peripheral Clocking ConsiderationsVideo Processing Back End Clocking Product Preview PLL Controller Pllc PLL Controller ModulePLLC1 10. PLLC1 Output ClocksPLLC1 Configuration In DM355 TMS320DM35511. PLLC2 Output Clocks PLLC2 Configuration in DM355PLLC2 SYSCLK1 DDR PHYPower and Sleep Controller PSC System Control Module12. Peripheral Pin Mux Overview Pin MultiplexingHardware Controlled Pin Multiplexing Peripheral Muxed With Primary Function Secondary Function14. Reset Types Device Reset13. Aecfg Async Emif Configuration Pin Mux Coding Software Controlled Pin Multiplexing15. Device Configuration Default Device ConfigurationsDevice Configuration Pins Device Configuration AffectedPLL Configuration Power Domain and Module State ConfigurationModule 16. Module ConfigurationDefault States Device Boot Modes ARM Boot Mode ConfigurationAemif Configuration Boot Modes Overview Power Management Boot Mode Functional Block Diagram17. Power Management Features Power Management Features DescriptionEdma Controller 14 64-Bit Crossbar ArchitectureCrossbar Connections 18. Crossbar Connection MatrixProduct Preview Edma Event Name Event Description Channel Edma Channel Synchronization Events19. Edma Channel Synchronization Events1 MPEG/JPEG Overview 19. Edma Channel Synchronization EventsDevice Operating Conditions VbusCV DD Recommended Operating ConditionsMIN NOM MAX Unit USB UsbvbusMIN TYP MAX Unit ParameterTest Conditions Tester PinElectronics Signal Transition LevelsParameter Information Device-Specific Information Output Under TestTiming Parameters and Board Routing Analysis Power Supplies Recommended Clock and Control Signal Transition BehaviorPower Supplies Tolerance PackagePower-Supply Decoupling Power-Supply SequencingPower-Supply Design Considerations Timing Requirements for Reset 1 2 see Figure ResetReset Electrical Data/Timing MINOscillators and Clocks 1 MXI1 24-MHz OscillatorESR 2 MXI2 27-MHz Oscillator optional oscillatorParameter MIN TYP MAX Unit MXI2 MXO2MIN TYP MAX Clock PLL Electrical Data/Timing Input and Output ClocksTiming Requirements for MXI1/CLKIN11 2 see Figure MXI/CLKINUNI MXI/CLKIN CLKOUT111. CLKOUT3 Timing 10. Timing Requirements for Gpio Inputs see Figure General-Purpose Input/Output GpioGpio Peripheral Input/Output Electrical Data/Timing MIN Unit MAXEXTINTx Gpio Peripheral External Interrupts Electrical Data/TimingGPIx GPOx Nand NAND, SmartMedia, xD External Memory Interface EmifAsynchronous Emif Aemif OneNANDMAX T ReadsWrites UNI MAX T DM355 MINNomRST*E WS+WST+WH*E WS+WST+WH+EWEmoe Output hold time, Emwe high to WH*E EMD150 invalid EMCE10EMA130 EMD150Emwe Emwait EMA130 EMD150Emoe Emwait 18. Synchronous OneNAND Flash Read Timing 2 DDR2 Memory Controller 2.1 DDR2/mDDR Memory Controller Electrical Data/TimingMMC/SD Fast Mode Standard Mode Unit MIN MAXParameter Fast Mode Standard Unit MIN MAX 1 MMC/SD Electrical Data/TimingSdclk Sdclk Sdcmd Start XmitEND Start ENDCCD Controller Ccdc Video Processing Sub-System Vpss OverviewVideo Processing Front-End Vpfe Ipipe Image Pipe SdramHardware 3A H3A Pclk DM355-216 DM355-270MIN MAX CWE/CFIELD HD/VD11,13 12,14 CI70/YI70 CCD130Video Processing Back-End Vpbe On-Screen Display OSDVideo Encoder / Digital LCD Controller VENC/DLCD CGMS/WSSPclk Extclk MINVctl B Vdatac VclkinaVctlb Vclkin a VclkMSB VrefibiasIout VFB 32. DAC With Buffer Circuit TvoutvParameter LOW Speed Full Speed High Speed Unit 10 USB10.1 USB2.0 Electrical Data/Timing MbpsUsbdp Usbdm10%V OL 90%V OH 26. Timing Requirements for UARTx Receive see Figure Universal Asynchronous Receiver/Transmitter UartUart Electrical Data/Timing 35. Uart Transmit/Receive Timing UARTTXDn UARTRXDn Start Bit DataBits28. Timing Requirements for SPI All Modes1 see Figure Serial Port Interface SPISPI Electrical Data/Timing SPIxCLK ClockPolarity=037. SPI Master Mode External Timing Clock Phase = SpienInput Spien SpiclkSpidi Msbin Data Lsbin Spido Msbout Data LsboutInter-Integrated Circuit I2C SDA SCL Standard Fast Mode Unit MIN MAX13.1 I2C Electrical Data/Timing Stop Start RepeatedStop Start 34. Switching Characteristics for I2C Timings1 see FigureParameter Standard Fast Mode Unit MIN MAX StopAudio Serial Port ASP ASP Electrical Data/Timing OtgclksFSX Clks ClkrClkx Master Unit MIN MAX 38. ASP as SPI Switching Characteristics137. ASP as SPI Timing Requirements Parameter Master Unit MIN MAXM34 M35 M42 40. ASP as SPI Switching Characteristics139. ASP as SPI Timing Requirements M37 M38 M36 Bit0 Bitn-1 M39 M40M43 M44 M52 42. ASP as SPI Switching Characteristics141. ASP as SPI Timing Requirements M46 M45 Bit0 Bitn-1 M49 M50M53 M54 M62 44. ASP as SPI Switching Characteristics143. ASP as SPI Timing Requirements M5645. Timing Requirements for Timer Input1 2 3 see Figure TimerTimer Electrical Data/Timing TiminPWM0/1/2/3 Pulse Width Modulator PWM16.1 PWM0/1/2/3 Electrical/Timing Data 48. PWM Output Delay Timing Vdccdc PWM0 Invalid PWM1 PWM2 PWM3 ValidRTO0/1/2/3 Real Time Out RTORTO Electrical/Timing Data RTO0Ieee 1149.1 Jtag TCK Rtck TDO TDI TMS Jtag Test-Port Electrical Data/Timing48. Timing Requirements for Jtag Test Port see Figure 52. Jtag Output Timing Rtck TDORevision History ADDS/CHANGES/DELETESRevision History Packaging Information Thermal Resistance Characteristics Pbga Package ZCEThermal Data for ZCE ΜC/WPage Rfid Products ApplicationsDSP