Texas Instruments TMS320DM355 warranty Arm, Vpss VCO, Plldiv Syscl Sysclk PLLDIV3 PLLDIV4

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TMS320DM355

Digital Media System-on-Chip (DMSoC)

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SPRS463A –SEPTEMBER 2007 –REVISED SEPTEMBER 2007

3.5.2.2Supported Clocking Configurations for DM355-216 (36 MHz reference)

3.5.2.2.1DM355-216 PLL1 (36 MHz reference)

All supported clocking configurations for DM355-216 PLL1 with 36 MHz reference clock are shown in Table 3-4

Table 3-4. PLL1 Supported Clocking Configurations DM355-216 (36 MHz reference)

PREDI	PLLM	POSTDIV	PLL1	ARM /		Peripherals		Venc		VPSS
V			VCO	MPEG and
				JPEG
				Co-Processor
(/8	(m	(/2 or /1	(MHz)	PLLDIV	SYSCL	PLLDIV	SYSCLK	PLLDIV3	SYSCLK	PLLDIV4	SYSCLK
fixed)	programmable	programma		1	K1	2	2	(/n	3	(/4 or /2	4
	)	ble)		(/2	(MHz)	(/4	(MHz)	programma	(MHz)	programmable	(MHz)
				fixed)		fixed)		ble)		)
bypass	bypass	bypass	bypass	2	18	4	9	10	3.6	4	9
8	96	1	432	2	216	4	108	16	27	4	108
8	180	2	405	2	202.5	4	101.25	15	27	4	101.25
8	168	2	378	2	189	4	94.5	14	27	4	94.5
8	156	2	351	2	175.5	4	87.75	13	27	4	87.75
8	144	2	324	2	162	4	81	12	27	4	81
8	132	2	297	2	148.5	4	74.25	11	27	4	74.25
8	120	2	270	2	135	4	67.5	10	27	2	135
8	108	2	243	2	121.5	4	60.75	9	27	2	121.5
8	96	2	216	2	108	4	54	8	27	2	108

3.5.2.2.2 DM355-216 PLL2 (36 MHz reference)

All supported clocking configurations for DM355-216 PLL2 with 36 MHz reference clock are shown in Table 3-5

Table 3-5. PLL2 Supported Clocking Configurations for DM355-216 (36 MHz reference)

PREDIV	PLLM	POSTDIV	PLL2 VCO	DDR PHY		DDR Clock
(/n programmable)	(m	(/1 fixed)	(MHz)	PLLDIV1	SYSCLK1	DDR_CLK
	programmable)			(/1 fixed)	(MHz)	(MHz)
bypass	bypass	bypass	bypass	1	36	18
12	114	1	342	1	342	171
12	108	1	324	1	324	162
12	102	1	306	1	306	153
12	96	1	288	1	288	144
18	133	1	266	1	266	133
27	150	1	200	1	200	100
27	120	1	160	1	160	80

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