Texas Instruments TMS320DM355 warranty Clks Clkr, Clkx, Fsx

TMS320DM355

Digital Media System-on-Chip (DMSoC)

www.ti.com

SPRS463A –SEPTEMBER 2007 –REVISED SEPTEMBER 2007

Table 5-36. Switching Characteristics Over Recommended Operating Conditions for ASP(1) (2)

(see Figure 5-41)

NO.

2 tc(CKRX)

17 td(CLKS-CLKRX)

3 tw(CKRX)

4td(CKRH-FRV)

9td(CKXH-FXV)

PARAMETER

Cycle time, CLKR/X

Delay time, CLKS high to internal CLKR/X

Pulse duration, CLKR/X high or CLKR/X low

Delay time, CLKR high to internal FSR valid

Delay time, CLKX high to internal FSX valid

	DM355	UNIT
	MIN
		MAX
CLKR/X int	38.5 or 2P(3)(4)	ns
CLKR/X int	1	24
CLKR/X int	C - 1	C + 1 ns
CLKR int	3	25
CLKR ext	3	ns
		25
CLKX int	-4	8
CLKX ext	3	ns
		25

12

tdis(CKXH- DXHZ)

Disable time, DX high impedance following last data bit from CLKX high

CLKX int		12	ns
CLKX ext		12	ns
CLKX int	-5	12	ns

13td(CKXH-DXV)

14td(FXH-DXV)

Delay time, CLKX high to DX valid

Delay time, FSX high to DX valid ONLY applies when in data delay 0 (XDATDLY = 00b) mode

CLKX ext	3	25 ns
FSX int		14(5)	ns
FSX ext		25(5)

(1)CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

(2)Minimum delay times also represent minimum output hold times.

(3)P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5) .

(4)Use which ever value is greater.

(5)Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR. if DXENA = 0, then D1 = D2 = 0

if DXENA = 1, then D1 = 4P, D2 = 8P

		15		16	16
CLKS
	17	2
		3	3
CLKR
		4	4
FSR￿(int)
		5		6
FSR￿(ext)
			7		8
DR				Bit(n-1)	(n-2)	(n-3)
	17	2
		3
			3
CLKX
		9
FSX￿(int)
		11
		10
FSX￿(ext)
FSX
(XDATDLY=00b)		12		14	13(A)
				13(A)
DX		Bit￿0		Bit(n-1)	(n-2)	(n-3)

A. Parameter￿No.￿13￿applies￿to￿the￿first￿data￿bitonly when￿XDATDLY ≠ 0.

Figure 5-41. ASP Timing

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