Device Clocking, Overview | Texas Instruments TMS320DM355 manual

TMS320DM355

Digital Media System-on-Chip (DMSoC)

www.ti.com

SPRS463A –SEPTEMBER 2007 –REVISED SEPTEMBER 2007

3.5 Device Clocking

3.5.1Overview

The DM355 requires one primary reference clock . The reference clock frequency may be generated either by crystal input or by external oscillator. The reference clock is the clock at the pins named MXI1/MXOI. The reference clock drives two separate PLL controllers (PLLC1 and PLLC2). PLLC1 generates the clocks required by the ARM, MPEG and JPEG co-processor, VPBE, VPSS, and peripherals. PLL2 generates the clock required by the DDR PHY. A block diagram of DM355'sclocking architecture is shown in Figure 5-1. The PLLs are described further in Section 3.6.

PRODUCT PREVIEW

Submit Documentation Feedback

Detailed Device Description

Page 65

Image 65

Texas Instruments TMS320DM355 warranty Device Clocking, Overview

TMS320DM355 specifications

The Texas Instruments TMS320DM355 is a versatile digital signal processor designed to support a wide array of multimedia applications, specifically in the realms of digital video and audio processing. As part of the TMS320 family of digital signal processors, the DM355 brings a blend of computational power, energy efficiency, and integrated features that make it highly effective for tasks such as video encoding, decoding, and general signal processing.

One of the standout features of the DM355 is its advanced DaVinci architecture, which is specifically optimized for multimedia tasks. This architecture integrates both DSP and application processing functionalities. The dual-core architecture includes a high-performance DSP core that specializes in real-time signal processing alongside an ARM926EJ-S RISC microprocessor, facilitating the execution of complex algorithms and control tasks.

The DM355 offers robust multimedia processing capabilities with support for several video formats, including MPEG-2, MPEG-4, H.264, and JPEG. This enables developers to create powerful video applications for a variety of devices, from industrial systems to consumer electronics. Its processing capabilities extend to audio processing, allowing it to efficiently handle audio codecs and enhance audio quality in applications ranging from IP cameras to set-top boxes.

In terms of connectivity, the TMS320DM355 supports various interfaces including USB 2.0, Ethernet, and various serial interfaces like UART, SPI, and I2C. This wide range of connectivity options ensures that the DM355 can easily interface with different peripherals and network components, making it a suitable choice for networked applications.

Energy efficiency is another significant advantage of the DM355. With a focus on low power consumption, the device is designed to operate effectively in battery-powered and heat-sensitive environments. Its low thermal design power allows for extended operational life and reduced thermal management requirements, making it ideal for portable devices.

Furthermore, the DM355 is supported by a comprehensive software development framework, including the TI Code Composer Studio and a range of middleware tools, which streamline application development and speed up time to market. Its rich ecosystem enhances its usability across different applications, ensuring that developers can leverage the full potential of the hardware.

In summary, the Texas Instruments TMS320DM355 stands out as a powerful yet cost-effective DSP solution, combining advanced multimedia processing capabilities, robust connectivity options, and energy efficiency. Its unique architecture and extensive support resources make it a preferred choice for developers seeking to create innovative multimedia solutions.

Contents

TMS320DM355 Digital Media System-on-Chip DMSoC Features TMS320DM355 Digital Media System-on-Chip DMSoC Description Functional Block Diagram Functional Block Diagram ARM926EJ-S Risc CPU Contents Characteristics of the Processor Device CharacteristicsHardware Features DM355 Memory Map Summary DM355 ARM Configuration Bus Access to PeripheralsDM355 Memory Map Edma USB Address Pin Map Bottom View Pin Assignments Pin Map Quadrant B Pin Map Quadrant C Pin Map Quadrant D Pin Functions CCD Controller Signals for Each Input ModeImage Data Input Video Processing Front End PIN Name CCD Terminal Name no CCD Controller/Video Input Terminal FunctionsType Description Camhd Image Data Output Video Processing Back End VpbeCamvd Camwen FIELD\ R5 GIO083 PCLK/ T3 GIO082 PIN Name Signals for Vpbe Display ModesYCC8 Prgb Srgb REC656 Terminal Name Digital Video Terminal Functions Analog Video Terminal Functions Asynchronous External Memory Interface AemifAsynchronous EMIF/NAND/OneNAND Terminal Functions Terminal Zvdd Type 1 Other 2EMBA1 EMBA0 10. DDR Terminal Functions DDR Memory Interface DDRDQ13 DDRDQ14DDRDQ12 DDRDQ11 11. Gpio Terminal Functions Gpio UART2C MMCSD1 UART2R MMCSD1ASP0FS ASP0CL Async Emif Data Bus bit01 GIO039 J17 PWM3B COUT1 Type 1 Other 2 3 Description Camwe Nfield / R5 GIO083 Camvd RTO0 COUT6PWM1 COUT7 SPI0SDI SPI2SDISPI2SDE 12. MMC/SD Terminal Functions Multi-Media Card/Secure Digital MMC/SD Interfaces Audio Interfaces Universal Serial Bus USB Interface13. USB Terminal Functions 14. ASP Terminal Functions 15. Uart Terminal Functions Uart Interface Serial Interface 10 I2C Interface16. I2C Terminal Functions 17. SPI Terminal Functions 18. Clocks Terminal Functions Clock Interface Pulse Width Modulator PWM Interface Real Time Output RTO Interface19. RTO Terminal Functions 20. PWM Terminal Functions 21. System/Boot Terminal Functions System Configuration InterfacePWM3B Field PWM3D 22. Emulation Terminal Functions Emulation BGA Pin List23. DM355 Pin Descriptions M4 I/O Ccdc GIOPINMUX08.CIN32 PINMUX09.CIN10 R3 I/O Ccdc Camvd Ccdc Camhd CcdcCamwenfie Ccdc PINMUX011.CAM PWM2B / RTO1 PWM2A / RTO0PWM2C / RTO2 PWM2D / RTO3 Reset Description Mux Control State Reset DescriptionName BGA Type Group GND Ddrd PWR DdriPWR Ddrd Ddrzn Ddri Aemi AECFG0 GIO GroupAECFG1 GIO PINMUX24.EMD1 PINMUX21.EMA0GIO EMIF2 PINMUX27.EMCE PINMUX25.EMD7PINMUX26.EMCE EOE GIO PINMUX28.EMWPINMUX29.EMW AIT GIO MMCSD1 DATA3 PINMUX398.GIO2 MMCSD1DATUART2RTS GIO Uart UART2 RTS MMCSD1DAT GIO SPI1SDENA1 PINMUX324.GIO1PINMUX327.GIO8 PINMUX328.GIO7 Usbdrvvbu Usbp Usbvbus UsbpGND Usbp PWR Usbp ASP1CLKX ResetASP1FSX ASP1CLKR Type Group RSV03 RSV04 RSV05 RSV06 RSV07Cvdd Cvdd PWR K10 Development Tools Device SupportDevice Nomenclature Software Development Tools Related Documentation From Texas Instruments Device Documentation Product Preview SPRUF71 Components of the ARM Subsystem ARM Subsystem Overview ARM926EJ-S Risc CPU Caches and Write Buffer 1 CP152 MMU Advanced High-performance Bus AHB Tightly Coupled Memory TCMEmbedded Trace Macrocell ETM and Embedded Trace Buffer ETB Memory Mapping Peripherals External MemoriesARM Interrupt Controller Aintc Interrupt Mapping Number Aintc Interrupt ConnectionsInterrupt Acronym Source Overview Device Clocking Preview Supported Clocking Configurations for DM355-216 Plldiv Syscl Sysclk PLLDIV3 PLLDIV4 ARMVpss VCO Pred Supported Clocking Configurations for DM355-270Mpeg and Jpeg PLLDIV1 Sysc Plldi SYSCLK2 PLLDIV3 Sysclk PLLDIV4 SYSCLK4 Plldiv Sysc SYSCLK2 PLLDIV3 Syscl PLLDIV4 SYSCLK4 Prediv PllmPostdi USB Clocking Peripheral Clocking ConsiderationsVideo Processing Back End Clocking Product Preview PLL Controller Module PLL Controller Pllc 10. PLLC1 Output Clocks PLLC1 TMS320DM355 PLLC1 Configuration In DM355 PLLC2 PLLC2 Configuration in DM35511. PLLC2 Output Clocks SYSCLK1 DDR PHY System Control Module Power and Sleep Controller PSC Hardware Controlled Pin Multiplexing Pin Multiplexing12. Peripheral Pin Mux Overview Peripheral Muxed With Primary Function Secondary Function 13. Aecfg Async Emif Configuration Pin Mux Coding Device Reset14. Reset Types Software Controlled Pin Multiplexing Device Configuration Pins Default Device Configurations15. Device Configuration Device Configuration Affected Power Domain and Module State Configuration PLL Configuration Module 16. Module ConfigurationDefault States Device Boot Modes ARM Boot Mode ConfigurationAemif Configuration Boot Modes Overview Boot Mode Functional Block Diagram Power Management Power Management Features Description 17. Power Management Features Crossbar Connections 14 64-Bit Crossbar ArchitectureEdma Controller 18. Crossbar Connection Matrix Product Preview Edma Event Name Event Description Channel Edma Channel Synchronization Events19. Edma Channel Synchronization Events1 19. Edma Channel Synchronization Events MPEG/JPEG Overview Vbus Device Operating Conditions MIN NOM MAX Unit Recommended Operating ConditionsCV DD USB Usbvbus MIN TYP MAX Unit ParameterTest Conditions Parameter Information Device-Specific Information Signal Transition LevelsTester PinElectronics Output Under Test Timing Parameters and Board Routing Analysis Power Supplies Recommended Clock and Control Signal Transition BehaviorPower Supplies Tolerance Package Power-Supply Decoupling Power-Supply SequencingPower-Supply Design Considerations Reset Electrical Data/Timing ResetTiming Requirements for Reset 1 2 see Figure MIN 1 MXI1 24-MHz Oscillator Oscillators and Clocks Parameter MIN TYP MAX Unit 2 MXI2 27-MHz Oscillator optional oscillatorESR MXI2 MXO2 Timing Requirements for MXI1/CLKIN11 2 see Figure Clock PLL Electrical Data/Timing Input and Output ClocksMIN TYP MAX MXI/CLKIN MXI/CLKIN CLKOUT1 UNI 11. CLKOUT3 Timing Gpio Peripheral Input/Output Electrical Data/Timing General-Purpose Input/Output Gpio10. Timing Requirements for Gpio Inputs see Figure MIN Unit MAX EXTINTx Gpio Peripheral External Interrupts Electrical Data/TimingGPIx GPOx Asynchronous Emif Aemif External Memory Interface EmifNand NAND, SmartMedia, xD OneNAND MAX T ReadsWrites RST*E DM355 MINNomUNI MAX T WS+WST+WH*E WS+WST+WH+EW EMA130 Output hold time, Emwe high to WH*E EMD150 invalid EMCE10Emoe EMD150 Emwe Emwait EMA130 EMD150Emoe Emwait 18. Synchronous OneNAND Flash Read Timing 2.1 DDR2/mDDR Memory Controller Electrical Data/Timing 2 DDR2 Memory Controller Parameter Fast Mode Standard Unit MIN MAX Fast Mode Standard Mode Unit MIN MAXMMC/SD 1 MMC/SD Electrical Data/Timing END Sdclk Sdcmd Start XmitSdclk Start END CCD Controller Ccdc Video Processing Sub-System Vpss OverviewVideo Processing Front-End Vpfe Sdram Ipipe Image Pipe Hardware 3A H3A Pclk DM355-216 DM355-270MIN MAX 11,13 12,14 HD/VDCWE/CFIELD CI70/YI70 CCD130 On-Screen Display OSD Video Processing Back-End Vpbe CGMS/WSS Video Encoder / Digital LCD Controller VENC/DLCD Pclk Extclk Vctl B Vdatac VclkinaVctlb Vclk Vclkin a MSB VrefibiasIout VFB Tvoutv 32. DAC With Buffer Circuit 10.1 USB2.0 Electrical Data/Timing 10 USBParameter LOW Speed Full Speed High Speed Unit Mbps Usbdp Usbdm10%V OL 90%V OH 26. Timing Requirements for UARTx Receive see Figure Universal Asynchronous Receiver/Transmitter UartUart Electrical Data/Timing UARTTXDn UARTRXDn Start Bit DataBits 35. Uart Transmit/Receive Timing SPI Electrical Data/Timing Serial Port Interface SPI28. Timing Requirements for SPI All Modes1 see Figure SPIxCLK ClockPolarity=0 Spien 37. SPI Master Mode External Timing Clock Phase = Spidi Msbin Data Lsbin Spien SpiclkInput Spido Msbout Data Lsbout Inter-Integrated Circuit I2C 13.1 I2C Electrical Data/Timing Standard Fast Mode Unit MIN MAXSDA SCL Stop Start Repeated Parameter Standard Fast Mode Unit MIN MAX 34. Switching Characteristics for I2C Timings1 see FigureStop Start Stop Audio Serial Port ASP Otgclks ASP Electrical Data/Timing FSX Clks ClkrClkx 37. ASP as SPI Timing Requirements 38. ASP as SPI Switching Characteristics1Master Unit MIN MAX Parameter Master Unit MIN MAX 39. ASP as SPI Timing Requirements 40. ASP as SPI Switching Characteristics1M34 M35 M42 M37 M38 M36 Bit0 Bitn-1 M39 M40 41. ASP as SPI Timing Requirements 42. ASP as SPI Switching Characteristics1M43 M44 M52 M46 M45 Bit0 Bitn-1 M49 M50 43. ASP as SPI Timing Requirements 44. ASP as SPI Switching Characteristics1M53 M54 M62 M56 Timer Electrical Data/Timing Timer45. Timing Requirements for Timer Input1 2 3 see Figure Timin PWM0/1/2/3 Pulse Width Modulator PWM16.1 PWM0/1/2/3 Electrical/Timing Data Vdccdc PWM0 Invalid PWM1 PWM2 PWM3 Valid 48. PWM Output Delay Timing RTO Electrical/Timing Data Real Time Out RTORTO0/1/2/3 RTO0 Ieee 1149.1 Jtag TCK Rtck TDO TDI TMS Jtag Test-Port Electrical Data/Timing48. Timing Requirements for Jtag Test Port see Figure Rtck TDO 52. Jtag Output Timing ADDS/CHANGES/DELETES Revision History Revision History Thermal Data for ZCE Thermal Resistance Characteristics Pbga Package ZCEPackaging Information ΜC/WPage Rfid Products ApplicationsDSP