Texas Instruments TMS320DM355 DM355 MINNom, Rst*E, Uni Max T, Ws+Wst+Wh*E Ws+Wst+Wh+Ew, Wst*E

th(EM_CLKH- EM_AIV)

tw(EM_CLKH) tw(EM_CLKL)

TMS320DM355

Digital Media System-on-Chip (DMSoC)

www.ti.com

SPRS463A –SEPTEMBER 2007 –REVISED SEPTEMBER 2007

Table 5-14. Switching Characteristics Over Recommended Operating Conditions for Asynchronous

Memory Cycles for AEMIF Module (see Figure 5-14and Figure 5-15) (continued)

NO.

6tsu(EMBAV-EMOEL)

7th(EMOEH-EMBAIV)

8tsu(EMBAV-EMOEL)

9th(EMOEH-EMAIV)

10 tw(EMOEL)

11td(EMWAITH-

EMOEH)

PARAMETER

Output setup time, EM_BA[1:0] valid to EM_OE low

Output hold time, EM_OE high to EM_BA[1:0] invalid

Output setup time, EM_A[13:0] valid to EM_OE low

Output hold time, EM_OE high to EM_A[13:0] invalid

EM_OE active low width (EW = 0)

EM_OE active low width (EW = 1)

Delay time from EM_WAIT deasserted to EM_OE high

DM355

MINNom

(RS)*E

(RH)*E

(RS)*E

(RH)*E

(RST)*E

(RST+(EWC*16))*E

4E

UNI

MAX T

ns

ns

ns

ns

ns ns

ns

READS (OneNAND Synchronous Burst Read)

PRODUCT PREVIEW

32 fc(EM_CLK)

33 tc(EM_CLK)

34tsu(EM_ADVV- EM_CLKH)

35 th(EM_CLKH- EM_ADVIV)

36tsu(EM_AV- EM_CLKH)

37

38

39

Frequency, EM_CLK

Cycle time, EM_CLK

Output setup time, EM_ADV valid before EM_CLK high

Output hold time, EM_CLK high to EM_ADV invalid

Output setup time, EM_A[13:0]/EM_BA[1] valid before EM_CLK high

Output hold time, EM_CLK high to

EM_A[13:0]/EM_BA[1] invalid

Pulse duration, EM_CLK high

Pulse duration, EM_CLK low

WRITES

1

15

5

6

5

6

tc(EM_CLK)/3 tc(EM_CLK)/3

66MH z

1000 ns ns

ns

ns

ns

ns ns

15tc(EMWCYCLE)

16tsu(EMCEL-EMWEL)

17th(EMWEH-EMCEH)

20tsu(EMBAV-EMWEL)

21th(EMWEH-EMBAIV)

22tsu(EMAV-EMWEL)

23th(EMWEH-EMAIV)

24 tw(EMWEL)

25td(EMWAITH-

EMWEH)

26tsu(EMDV-EMWEL)

EMIF write cycle time (EW = 0)

EMIF write cycle time (EW = 1)

Output setup time, EM_CE[1:0] low to EM_WE low (SS = 0)

Output setup time, EM_CE[1:0] low to EM_WE low (SS = 1)

Output hold time, EM_WE high to EM_CE[1:0] high (SS = 0)

Output hold time, EM_WE high to EM_CE[1:0] high (SS = 1)

Output setup time, EM_BA[1:0] valid to EM_WE low

Output hold time, EM_WE high to EM_BA[1:0] invalid

Output setup time, EM_A[13:0] valid to EM_WE low

Output hold time, EM_WE high to EM_A[13:0] invalid

EM_WE active low width (EW = 0)

EM_WE active low width (EW = 1)

Delay time from EM_WAIT deasserted to EM_WE high

Output setup time, EM_D[15:0] valid to EM_WE low

(WS+WST+WH)*E

(WS+WST+WH+(EW

C*16))*E

(WS)*E

0

(WH)*E

0

(WS)*E

(WH)*E

(WS)*E

(WH)*E

(WST)*E

(WST+(EWC*16))*E

4E

(WS)*E

ns ns

ns

ns

ns

ns

ns

ns

ns

ns

ns ns

ns

ns

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