Texas Instruments TMS320DM355 warranty Reads, Writes, Max T

TMS320DM355

Digital Media System-on-Chip (DMSoC)

www.ti.com

SPRS463A –SEPTEMBER 2007 –REVISED SEPTEMBER 2007

5.7.1.3AEMIF Electrical Data/Timing

Table 5-13. Timing Requirements for Asynchronous Memory Cycles for AEMIF Module(1) (see Figure 5-14

and Figure 5-15)

NO

.

2tw(EM_WAIT)

12tsu(EMDV-EMOEH)

13th(EMOEH-EMDIV)

14 tsu(EMOEL-

EMWAIT)

	MIN
READS and WRITES
Pulse duration, EM_WAIT assertion and	2E
deassertion
READS
Setup time, EM_D[15:0] valid before EM_OE high	5
Hold time, EM_D[15:0] valid after EM_OE high	0
Delay time from EM_OE low to EM_WAIT
asserted(2)

READS (OneNAND Synchronous Burst Read)

Setup time, EM_D[15:0] valid before EM_CLK

DM355

UNIT

NomMAX

ns

ns

ns

4E ns

30 tsu(EMDV-EMCLKH)

high

4

ns

31 th(EMCLKH-EMDIV)

Hold time, EM_D[15:0] valid after EM_CLK high 4

WRITES

ns

28	tsu(EMWEL-	Delay time from EM_WE low to EM_WAIT	4E	ns
	EMWAIT)	asserted(2)

(1)E = PLLC1 SYSCLK2 period in ns. SYSCLK2 is the EMIF peripheral clock. SYSCLK2 is one-fourth the PLLC output clock. For example, when PLLC output clock = 432 MHz, E = 9.259 ns. See Section 3.5 for more information.

(2)Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended wait states. Figure 5-16and Figure 5-17describe EMIF transactions that include extended wait states inserted during the STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where the HOLD phase would begin if there were no extended wait cycles.

Table 5-14. Switching Characteristics Over Recommended Operating Conditions for Asynchronous

Memory Cycles for AEMIF Module(1) (2) (3) (see Figure 5-14and Figure 5-15)

PRODUCT PREVIEW

NO.	DM355		UNI
	PARAMETER	Nom	MAX T
	MIN
	READS and WRITES
1 td(TURNAROUND)	Turn around time	(TA)*E	ns
	READS

3 tc(EMRCYCLE)

EMIF read cycle time (EW = 0)

(RS+RST+RH)*Ens

(RS+RST+RH+(EWC*

EMIF read cycle time (EW = 1)

16))*E

ns

Output setup time, EM_CE[1:0] low to EM_OE low (SS = 0)

(RS)*Ens

4 tsu(EMCEL-EMOEL)

Output setup time, EM_CE[1:0] low to

EM_OE low (SS = 1)

0ns

5 th(EMOEH-EMCEH)

Output hold time, EM_OE high to EM_CE[1:0] high (SS = 0)

Output hold time, EM_OE high to EM_CE[1:0] high (SS = 1)

(RH)*Ens

0ns

(1)TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold, MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-1], RH[8-1], WS[16-1], WST[64-1], WH[8-1], and MEW[1-256]. See the TMS320DM355 DMSoC Asynchronous External Memory Interface (EMIF) User'sGuide (SPRUED1) for more information.

(2)E = PLLC1 SYSCLK2 period in ns. SYSCLK2 is the EMIF peripheral clock. SYSCLK2 is one-fourth the PLLC output clock. For example, when PLLC output clock = 432 MHz, E = 9.259 ns. See Section 3.5 for more information

(3)EWC = external wait cycles determined by EM_WAIT input signal. EWC supports the following range of values EWC[256-1]. Note that the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See the TMS320DM355 DMSoC Asynchronous External Memory Interface (EMIF) User'sGuide (SPRUED1) for more information.

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